motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and ! are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. ?motorola, inc. 1996 mc68331 user s manual
mc68331 motorola user? manual iii paragraph title page section 1introduction section 2nomenclature 2.1 symbols and operators .................................................................................. 2-1 2.2 cpu32 registers ............................................................................................ 2-2 2.3 pin and signal mnemonics ............................................................................. 2-3 2.4 register mnemonics ....................................................................................... 2-5 2.5 conventions ................................................................................................... 2-6 section 3overview 3.1 mcu features ................................................................................................ 3-1 3.1.1 system integration module (sim) ........................................................... 3-1 3.1.2 central processing unit (cpu32) ........................................................... 3-1 3.1.3 queued serial module (qsm) ................................................................ 3-1 3.1.4 general-purpose timer (gpt) ............................................................... 3-2 3.2 system block diagram and pin assignment diagrams .................................. 3-2 3.3 pin descriptions ............................................................................................. 3-5 3.4 signal descriptions ......................................................................................... 3-7 3.5 intermodule bus ........................................................................................... 3-10 3.6 system memory map ................................................................................... 3-10 3.6.1 internal register map ........................................................................... 3-10 3.6.2 address space maps ........................................................................... 3-10 3.7 system reset ............................................................................................... 3-16 3.7.1 sim reset mode selection ................................................................... 3-16 3.7.2 mcu module pin function during reset ............................................. 3-17 section 4 system integration module 4.1 general ........................................................................................................... 4-1 4.2 system configuration and protection ............................................................. 4-2 4.2.1 module mapping ..................................................................................... 4-3 4.2.2 interrupt arbitration ................................................................................. 4-3 4.2.3 show internal cycles .............................................................................. 4-4 4.2.4 factory test mode ................................................................................. 4-4 4.2.5 register access ..................................................................................... 4-4 4.2.6 reset status ........................................................................................... 4-4 4.2.7 bus monitor ............................................................................................ 4-4 4.2.8 halt monitor ............................................................................................ 4-5 4.2.9 spurious interrupt monitor ...................................................................... 4-5 4.2.10 software watchdog ................................................................................ 4-5 table of contents
motorola mc68331 iv user? manual table of contents (continued) paragraph title page 4.2.11 periodic interrupt timer .......................................................................... 4-7 4.2.12 low-power stop operation .................................................................. 4-8 4.2.13 freeze operation ................................................................................... 4-9 4.3 system clock ................................................................................................. 4-9 4.3.1 clock sources ...................................................................................... 4-10 4.3.2 clock synthesizer operation ................................................................ 4-10 4.3.3 external bus clock ............................................................................... 4-15 4.3.4 low-power operation ........................................................................... 4-15 4.3.5 loss of reference signal ..................................................................... 4-16 4.4 external bus interface .................................................................................. 4-17 4.4.1 bus signals .......................................................................................... 4-18 4.4.1.1 address bus ................................................................................. 4-18 4.4.1.2 address strobe ............................................................................ 4-18 4.4.1.3 data bus ...................................................................................... 4-18 4.4.1.4 data strobe .................................................................................. 4-18 4.4.1.5 read/write signal ........................................................................ 4-18 4.4.1.6 size signals ................................................................................. 4-18 4.4.1.7 function codes ............................................................................ 4-19 4.4.1.8 data and size acknowledge signals ........................................... 4-19 4.4.1.9 bus error signal ........................................................................... 4-19 4.4.1.10 halt signal .................................................................................... 4-20 4.4.1.11 autovector signal ......................................................................... 4-20 4.4.2 dynamic bus sizing ............................................................................. 4-20 4.4.3 operand alignment .............................................................................. 4-21 4.4.4 misaligned operands ........................................................................... 4-21 4.4.5 operand transfer cases ...................................................................... 4-22 4.5 bus operation .............................................................................................. 4-22 4.5.1 synchronization to clkout ................................................................ 4-23 4.5.2 regular bus cycles .............................................................................. 4-23 4.5.2.1 read cycle ................................................................................... 4-24 4.5.2.2 write cycle ................................................................................... 4-25 4.5.3 fast termination cycles ....................................................................... 4-25 4.5.4 cpu space cycles ............................................................................... 4-26 4.5.4.1 breakpoint acknowledge cycle .................................................... 4-27 4.5.4.2 lpstop broadcast cycle ............................................................ 4-30 4.5.5 bus exception control cycles .............................................................. 4-30 4.5.5.1 bus errors .................................................................................... 4-32 4.5.5.2 double bus faults ........................................................................ 4-32 4.5.5.3 retry operation ............................................................................ 4-33 4.5.5.4 halt operation .............................................................................. 4-33 4.5.6 external bus arbitration ........................................................................ 4-34
mc68331 motorola user? manual v table of contents (continued) paragraph title page 4.5.6.1 slave (factory test) mode arbitration ......................................... 4-35 4.5.6.2 show cycles ................................................................................ 4-35 4.6 reset ............................................................................................................ 4-36 4.6.1 reset exception processing ................................................................ 4-36 4.6.2 reset control logic .............................................................................. 4-37 4.6.3 reset mode selection .......................................................................... 4-37 4.6.3.1 data bus mode selection ............................................................. 4-38 4.6.3.2 clock mode selection .................................................................. 4-40 4.6.3.3 breakpoint mode selection .......................................................... 4-40 4.6.4 mcu module pin function during reset ............................................. 4-40 4.6.5 pin state during reset ......................................................................... 4-41 4.6.5.1 reset states of sim pins ............................................................. 4-41 4.6.5.2 reset states of pins assigned to other mcu modules ............... 4-42 4.6.6 reset timing ........................................................................................ 4-42 4.6.7 power-on reset ................................................................................... 4-43 4.6.8 reset processing summary ................................................................. 4-44 4.6.9 reset status register .......................................................................... 4-45 4.7 interrupts ...................................................................................................... 4-45 4.7.1 interrupt exception processing ............................................................ 4-45 4.7.2 interrupt priority and recognition ......................................................... 4-45 4.7.3 interrupt acknowledge and arbitration ................................................. 4-46 4.7.4 interrupt processing summary ............................................................. 4-47 4.7.5 interrupt acknowledge bus cycles ....................................................... 4-48 4.8 chip selects ................................................................................................. 4-48 4.8.1 chip-select registers ........................................................................... 4-50 4.8.1.1 chip-select pin assignment registers ........................................ 4-51 4.8.1.2 chip-select base address registers ........................................... 4-52 4.8.1.3 chip-select option registers ....................................................... 4-52 4.8.1.4 portc data register .................................................................. 4-54 4.8.2 chip-select operation .......................................................................... 4-54 4.8.3 using chip-select signals for interrupt acknowledge .......................... 4-54 4.8.4 chip-select reset operation ................................................................ 4-55 4.9 parallel input/output ports ........................................................................... 4-57 4.9.1 pin assignment registers .................................................................... 4-57 4.9.2 data direction registers ...................................................................... 4-57 4.9.3 data registers ...................................................................................... 4-57 4.10 factory test ................................................................................................. 4-57 section 5 central processing unit 5.1 general ........................................................................................................... 5-1 5.2 cpu32 registers ............................................................................................ 5-2
motorola mc68331 vi user? manual table of contents (continued) paragraph title page 5.2.1 data registers ........................................................................................ 5-4 5.2.2 address registers .................................................................................. 5-5 5.2.3 program counter .................................................................................... 5-6 5.2.4 control registers .................................................................................... 5-6 5.2.4.1 status register ............................................................................... 5-6 5.2.4.2 alternate function code registers ................................................ 5-6 5.2.5 vector base register (vbr) ................................................................... 5-7 5.3 memory organization ..................................................................................... 5-7 5.4 virtual memory ............................................................................................... 5-9 5.5 addressing modes .......................................................................................... 5-9 5.6 processing states .......................................................................................... 5-9 5.7 privilege levels ............................................................................................ 5-10 5.8 instructions ................................................................................................... 5-10 5.8.1 m68000 family compatibility ............................................................... 5-14 5.8.2 special control instructions .................................................................. 5-14 5.8.2.1 low power stop (lpstop) ......................................................... 5-14 5.8.2.2 table lookup and interpolate (tbl) ............................................ 5-14 5.9 exception processing ................................................................................... 5-14 5.9.1 exception vectors ................................................................................ 5-15 5.9.2 types of exceptions ............................................................................. 5-16 5.9.3 exception processing sequence .......................................................... 5-17 5.10 development support ................................................................................... 5-17 5.10.1 m68000 family development support ................................................. 5-17 5.10.2 background debugging mode .............................................................. 5-18 5.10.2.1 enabling bdm .............................................................................. 5-19 5.10.2.2 bdm sources ............................................................................... 5-19 5.10.2.3 entering bdm ............................................................................... 5-20 5.10.2.4 bdm commands .......................................................................... 5-21 5.10.2.5 background mode registers ........................................................ 5-21 5.10.2.6 returning from bdm .................................................................... 5-22 5.10.2.7 serial interface ............................................................................. 5-22 5.10.2.8 recommended bdm connection ................................................. 5-24 5.10.3 deterministic opcode tracking ............................................................ 5-24 5.10.4 on-chip breakpoint hardware ............................................................. 5-25 5.11 loop mode instruction execution ................................................................. 5-25 section 6queued serial module 6.1 general ........................................................................................................... 6-1 6.2 qsm registers and address map .................................................................. 6-2 6.2.1 qsm global registers ............................................................................ 6-2 6.2.1.1 low-power stop operation ............................................................ 6-2
mc68331 motorola user? manual vii table of contents (continued) paragraph title page 6.2.1.2 freeze operation ........................................................................... 6-3 6.2.1.3 qsm interrupts ............................................................................... 6-3 6.2.2 qsm pin control registers .................................................................... 6-4 6.3 queued serial peripheral interface ................................................................ 6-5 6.3.1 qspi registers ....................................................................................... 6-6 6.3.1.1 control registers ........................................................................... 6-7 6.3.1.2 status register ............................................................................... 6-7 6.3.2 qspi ram .............................................................................................. 6-7 6.3.2.1 receive ram ................................................................................. 6-8 6.3.2.2 transmit ram ................................................................................ 6-8 6.3.2.3 command ram .............................................................................. 6-8 6.3.3 qspi pins ............................................................................................... 6-8 6.3.4 qspi operation ...................................................................................... 6-9 6.3.5 qspi operating modes ........................................................................ 6-10 6.3.5.1 master mode ................................................................................ 6-17 6.3.5.2 master wraparound mode ........................................................... 6-19 6.3.5.3 slave mode .................................................................................. 6-20 6.3.5.4 slave wraparound mode ............................................................. 6-21 6.3.6 peripheral chip selects ........................................................................ 6-21 6.4 serial communication interface ................................................................... 6-22 6.4.1 sci registers ....................................................................................... 6-22 6.4.1.1 control registers ......................................................................... 6-22 6.4.1.2 status register ............................................................................. 6-25 6.4.1.3 data register ............................................................................... 6-25 6.4.2 sci pins ............................................................................................... 6-25 6.4.3 sci operation ....................................................................................... 6-25 6.4.3.1 definition of terms ....................................................................... 6-26 6.4.3.2 serial formats .............................................................................. 6-26 6.4.3.3 baud clock ................................................................................... 6-26 6.4.3.4 parity checking ............................................................................ 6-27 6.4.3.5 transmitter operation .................................................................. 6-27 6.4.3.6 receiver operation ...................................................................... 6-29 6.4.3.7 idle-line detection ....................................................................... 6-29 6.4.3.8 receiver wakeup ......................................................................... 6-30 6.4.3.9 internal loop ................................................................................ 6-31 6.5 qsm initialization ......................................................................................... 6-31 section 7general-purpose timer 7.1 general ........................................................................................................... 7-1 7.2 gpt registers and address map ................................................................... 7-2 7.3 special modes of operation ........................................................................... 7-3
motorola mc68331 viii user? manual table of contents (continued) paragraph title page 7.3.1 low-power stop mode ........................................................................... 7-3 7.3.2 freeze mode .......................................................................................... 7-3 7.3.3 single-step mode ................................................................................... 7-3 7.3.4 test mode .............................................................................................. 7-4 7.4 polled and interrupt-driven operation ............................................................ 7-4 7.4.1 polled operation ..................................................................................... 7-4 7.4.2 gpt interrupts ........................................................................................ 7-5 7.5 pin descriptions ............................................................................................. 7-6 7.5.1 input capture pins (ic[1:3]) .................................................................... 7-6 7.5.2 input capture/output compare pin (ic4/oc5) ...................................... 7-6 7.5.3 output compare pins (oc[1:4]) ............................................................. 7-6 7.5.4 pulse accumulator input pin (pai) ......................................................... 7-7 7.5.5 pulse-width modulation (pwma, pwmb) .............................................. 7-7 7.5.6 auxiliary timer clock input (pclk) ........................................................ 7-7 7.6 general-purpose i/o ...................................................................................... 7-7 7.7 prescaler ........................................................................................................ 7-8 7.8 capture/compare unit ................................................................................... 7-9 7.8.1 timer counter ...................................................................................... 7-11 7.8.2 input capture functions ....................................................................... 7-11 7.8.3 output compare functions .................................................................. 7-12 7.8.3.1 output compare 1 ........................................................................ 7-13 7.8.3.2 forced output compare .............................................................. 7-13 7.9 input capture 4/output compare 5 .............................................................. 7-13 7.10 pulse accumulator ....................................................................................... 7-14 7.11 pulse-width modulation unit ........................................................................ 7-15 7.11.1 pwm counter ....................................................................................... 7-16 7.11.2 pwm function ...................................................................................... 7-17 appendix a electrical characteristics appendix b mechanical data and ordering information appendix cdevelopment support c.1 M68MMDS1632 modular development system ...................................... c-1 c.2 m68mevb1632 modular evaluation board .............................................. c-2 appendix d register summary d.1 central processing unit ............................................................................ d-1 d.1.1 cpu32 register model ..................................................................... d-2 d.1.2 ?status register ............................................................................ d-3
mc68331 motorola user? manual ix table of contents (continued) paragraph title page d.2 general-purpose timer ............................................................................ d-4 d.2.1 gptmcr ?gpt module configuration register ............................ d-4 d.2.2 gptmtr ?gpt module test register (reserved) ........................ d-5 d.2.3 icr ?gpt interrupt configuration register .................................... d-5 d.2.4 ddrgp ?port gp data direction register..................................... d-6 d.2.5 oc1m?oc1 action mask register ................................................. d-6 d.2.6 tcnt ?timer counter register ..................................................... d-6 d.2.7 pactl ?pulse accumulator control register ................................ d-7 d.2.8 tic[1:3] ?input capture registers 1? .......................................... d-8 d.2.9 toc[1:4] ?output compare registers 1? ................................... d-8 d.2.10 ti4/o5 ?input capture 4/output compare 5 register .................... d-8 d.2.11 tctl1/tctl2 ?timer control registers 1 and 2........................... d-8 d.2.12 tmsk1/tmsk2 ?timer interrupt mask registers 1 and 2 ............. d-9 d.2.13 tflg1/tflg2 ?timer interrupt flag registers 1 and 2.............. d-10 d.2.14 cforc ?compare force register............................................... d-10 d.2.15 pwma/pwmb ?pwm registers a/b ........................................... d-12 d.2.16 pwmcnt ?pwm count register ............................................... d-12 d.2.17 pwmbufa ?pwm buffer register a .......................................... d-12 d.2.18 prescl ?gpt prescaler ............................................................ d-12 d.3 system integration module ..................................................................... d-13 d.3.1 simcr ?module configuration register ...................................... d-14 d.3.2 simtr ?system integration test register ................................... d-15 d.3.3 syncr ?clock synthesizer control register ............................. d-15 d.3.4 rsr ?reset status register ....................................................... d-16 d.3.5 simtre ?system integration test register (eclk) .................... d-17 d.3.6 porte0/porte1 ?port e data register .................................... d-17 d.3.7 ddre ?port e data direction register ........................................ d-17 d.3.8 pepar ?port e pin assignment register .................................... d-17 d.3.9 portf0/portf1 ?port f data register..................................... d-18 d.3.10 ddrf ?port f data direction register......................................... d-18 d.3.11 pfpar ?port f pin assignment register..................................... d-18 d.3.12 sypcr ?system protection control register .............................. d-19 d.3.13 picr ?periodic interrupt control register.................................... d-20 d.3.14 pitr ?periodic interrupt timer register ...................................... d-20 d.3.15 swsr ?software service register .............................................. d-21 d.3.16 tstmsra ?master shift register a............................................. d-21 d.3.17 tstmsrb ?master shift register b............................................. d-21 d.3.18 tstsc ?test module shift count ................................................ d-21 d.3.19 tstrc ?test module repetition count ....................................... d-21 d.3.20 creg ?test submodule control register .................................. d-21 d.3.21 dreg ?distributed register......................................................... d-21
motorola mc68331 x user? manual table of contents (continued) paragraph title page d.3.22 portc ?port c data register ..................................................... d-21 d.3.23 cspar0 ?chip select pin assignment register 0....................... d-21 d.3.24 cspar1 ?chip select pin assignment register 1....................... d-22 d.3.25 csbarbt ?chip select base address register boot rom ....... d-23 d.3.26 csorbt ?chip select option register boot rom...................... d-23 d.4 queued serial module ............................................................................ d-25 d.4.1 qsmcr ?qsm configuration register ........................................ d-25 d.4.2 qtest ?qsm test register ........................................................ d-26 d.4.3 qilr ?qsm interrupt level register............................................ d-26 d.4.4 sccr0 ?sci control register 0 .................................................. d-27 d.4.5 sccr1 ?sci control register 1................................................... d-27 d.4.6 scsr ?sci status register ......................................................... d-29 d.4.7 scdr ?sci data register............................................................ d-30 d.4.8 portqs ?port qs data register ............................................... d-30 d.4.9 pqspar ?port qs pin assignment register ........................... d-30 d.4.10 spcr0 ?qspi control register 0 ................................................ d-32 d.4.11 spcr1 ?qspi control register 1 ............................................... d-33 d.4.12 spcr2 ?qspi control register 2 ............................................... d-34 d.4.13 spcr3 ?qspi control register 3 ............................................... d-34 d.4.14 rr[0:f] ?receive data ram........................................................ d-35 d.4.15 tr[0:f] ?transmit data ram ...................................................... d-35 d.4.16 cr[0:f] ?command ram............................................................. d-36
mc68331 motorola user? manual xi figure title page 3-1 mcu block diagram........................................................................................ 3-3 3-2 pin assignments for 132-pin package ............................................................ 3-4 3-3 pin assignments for 144-pin package ............................................................ 3-5 3-4 internal register memory map ...................................................................... 3-11 3-5 overall memory map ..................................................................................... 3-12 3-6 separate supervisor and user space map................................................... 3-13 3-7 supervisor space (separate program/data space) map ............................. 3-14 3-8 user space (separate program/data space) map ....................................... 3-15 4-1 system integration module block diagram ..................................................... 4-2 4-2 system configuration and protection.............................................................. 4-3 4-3 periodic interrupt timer and software watchdog timer ................................. 4-7 4-4 system clock block diagram .......................................................................... 4-9 4-5 system clock oscillator circuit ..................................................................... 4-10 4-6 system clock filter networks ....................................................................... 4-11 4-7 mcu basic system ....................................................................................... 4-17 4-8 operand byte order ...................................................................................... 4-21 4-9 word read cycle flowchart.......................................................................... 4-24 4-10 write cycle flowchart ................................................................................... 4-25 4-11 cpu space address encoding ..................................................................... 4-27 4-12 breakpoint operation flowchart.................................................................... 4-29 4-13 lpstop interrupt mask level....................................................................... 4-30 4-14 bus arbitration flowchart for single request................................................ 4-35 4-15 data bus mode select conditioning.............................................................. 4-39 4-16 power-on reset............................................................................................ 4-44 4-17 basic mcu system ....................................................................................... 4-49 4-18 chip-select circuit block diagram ................................................................ 4-50 4-19 cpu space encoding for interrupt acknowledge.......................................... 4-55 5-1 cpu32 block diagram .................................................................................... 5-2 5-2 user programming model ............................................................................... 5-3 5-3 supervisor programming model supplement.................................................. 5-3 5-4 data organization in data registers............................................................... 5-5 5-5 address organization in address registers.................................................... 5-5 5-6 memory operand addressing ......................................................................... 5-8 5-7 common in-circuit emulator diagram .......................................................... 5-18 5-8 bus state analyzer configuration ................................................................. 5-19 5-9 debug serial i/o block diagram ................................................................... 5-23 5-10 bdm serial data word .................................................................................. 5-24 5-11 bdm connector pinout.................................................................................. 5-24 5-12 loop mode instruction sequence.................................................................. 5-25 6-1 qsm block diagram........................................................................................ 6-1 6-2 qspi block diagram ....................................................................................... 6-6 list of illustrations
motorola mc68331 xii user? manual (continued) figure title page list of illustrations 6-3 qspi ram....................................................................................................... 6-7 6-4 flowchart of qspi initialization operation..................................................... 6-11 6-5 flowchart of qspi master operation (part 1) ............................................... 6-12 6-5 flowchart of qspi master operation (part 2) ............................................... 6-13 6-5 flowchart of qspi master operation (part 3) ............................................... 6-14 6-6 flowchart of qspi slave operation (part 1) ................................................. 6-15 6-6 flowchart of qspi slave operation (part 2) ................................................. 6-16 6-7 sci transmitter block diagram..................................................................... 6-23 6-8 sci receiver block diagram......................................................................... 6-24 7-1 gpt block diagram......................................................................................... 7-2 7-2 prescaler block diagram................................................................................. 7-9 7-3 capture/compare unit block diagram .......................................................... 7-10 7-4 input capture timing example...................................................................... 7-12 7-5 pulse accumulator block diagram ................................................................ 7-15 7-6 pwm block diagram ..................................................................................... 7-16 a-1 clkout output timing diagram.................................................................. a-12 a-2 external clock input timing diagram............................................................ a-12 a-3 eclk output timing diagram....................................................................... a-12 a-4 read cycle timing diagram ......................................................................... a-13 a-5 write cycle timing diagram.......................................................................... a-14 a-6 fast termination read cycle timing diagram ............................................. a-15 a-7 fast termination write cycle timing diagram.............................................. a-16 a-8 bus arbitration timing diagram ?active bus case .................................... a-17 a-9 bus arbitration timing diagram ?idle bus case ........................................ a-18 a-10 show cycle timing diagram ......................................................................... a-18 a-11 chip select timing diagram.......................................................................... a-19 a-12 reset and mode select timing diagram....................................................... a-19 a-13 background debugging mode timing diagram?erial communication...... a-21 a-14 background debugging mode timing diagram ?reeze assertion............. a-21 a-15 eclk timing diagram................................................................................... a-23 a-16 qspi timing ?master, cpha = 0 ............................................................... a-25 a-17 qspi timing ?master, cpha = 1 ............................................................... a-25 a-18 qspi timing ?slave, cpha = 0 ................................................................. a-26 a-19 qspi timing ?slave, cpha = 1 ................................................................. a-26 b-1 132-pin plastic surface mount package pin assignments ............................. b-2 b-2 144-pin plastic surface mount package pin assignments ............................. b-3 d-1 user programming model ...............................................................................d-2 d-2 supervisor programming model supplement..................................................d-2
mc68331 motorola user? manual xiii table title page 3-1 mcu driver types .......................................................................................... 3-6 3-2 mcu pin characteristics ................................................................................ 3-6 3-3 mcu power connections ............................................................................... 3-7 3-4 signal characteristics ..................................................................................... 3-7 3-5 signal function ............................................................................................... 3-8 3-6 sim reset mode selection ........................................................................... 3-16 3-7 module pin functions ................................................................................... 3-17 4-1 show cycle enable bits ................................................................................. 4-4 4-2 bus monitor period ......................................................................................... 4-5 4-3 modclk pin and swp bit during reset ...................................................... 4-6 4-4 software watchdog ratio ............................................................................... 4-6 4-5 modclk pin and ptp bit at reset ............................................................... 4-7 4-6 periodic interrupt priority ................................................................................ 4-8 4-7 clock control multipliers ............................................................................... 4-12 4-8 system frequencies from 32.768-khz reference ....................................... 4-14 4-9 clock control ................................................................................................ 4-16 4-10 size signal encoding ................................................................................... 4-19 4-11 address space encoding ............................................................................. 4-19 4-12 effect of dsack signals .............................................................................. 4-20 4-13 operand transfer cases .............................................................................. 4-22 4-14 dsack, berr, and halt assertion results ............................................. 4-31 4-15 reset source summary ............................................................................... 4-37 4-16 reset mode selection .................................................................................. 4-38 4-17 module pin functions ................................................................................... 4-41 4-18 sim pin reset states ................................................................................... 4-42 4-19 chip-select pin functions ............................................................................ 4-51 4-20 pin assignment field encoding .................................................................... 4-51 4-21 block size encoding ..................................................................................... 4-52 4-22 option register function summary ............................................................. 4-53 4-23 chip select base and option register reset values .................................. 4-56 4-24 csboot base and option register reset values ..................................... 4-57 5-1 instruction set summary .............................................................................. 5-11 5-2 exception vector assignments ..................................................................... 5-16 5-3 bdm source summary ................................................................................. 5-19 5-4 polling the bdm entry source ...................................................................... 5-20 5-5 background mode command summary ...................................................... 5-21 5-6 cpu generated message encoding ............................................................ 5-24 6-1 qsm pin function .......................................................................................... 6-4 6-2 qspi pin function .......................................................................................... 6-9 6-3 bits encoding ............................................................................................. 6-18 6-4 sci pin function .......................................................................................... 6-25 list of tables
motorola mc68331 xiv user? manual (continued) table title page list of tables 6-5 serial frame formats ...................................................................................6-26 6-6 effect of parity checking on data size .........................................................6-27 7-1 gpt status flags ............................................................................................7-4 7-2 gpt interrupt sources ....................................................................................7-5 7-3 pwm frequency ranges using 16.78-mhz/20.97-mhz system clocks ......7-17 a-1 maximum ratings .......................................................................................... a-1 a-2 typical ratings, 16.78 mhz operation .......................................................... a-2 a-2 typical ratings, 20.97 mhz operation ......................................................... a-2 a-3 thermal characteristics ................................................................................. a-3 a-4 16.78 mhz clock control timing ................................................................... a-3 a-4 20.97 mhz clock control timing ................................................................... a-4 a-5 16.78 mhz dc characteristics ....................................................................... a-5 a-5 20.97 mhz dc characteristics ....................................................................... a-6 a-6 16.78 mhz ac timing .................................................................................... a-8 a-6 20.97 mhz ac timing .................................................................................... a-9 a-7 background debugging mode timing .......................................................... a-20 a-8 16.78 mhz eclk bus timing ...................................................................... a-22 a-8 20.97 mhz eclk bus timing ...................................................................... a-22 a-9 qspi timing ................................................................................................. a-24 b-1 mcu ordering information ............................................................................. b-4 b-2 quantity order suffix ...................................................................................... b-4 c-1 mc68331 development tools ........................................................................ c-1 d-1 module address map ..................................................................................... d-1 d-2 gpt address map .......................................................................................... d-4 d-3 sim address map ......................................................................................... d-13 d-4 port e pin assignments ............................................................................... d-18 d-5 port f pin assignments ................................................................................ d-19 d-6 software watchdog ratio ............................................................................ d-19 d-7 bus monitor period ....................................................................................... d-20 d-8 cspar0 pin assignments ........................................................................... d-22 d-9 cspar1 pin assignments ........................................................................... d-22 d-10 cspar0 and cspar1 pin assignment field encoding .............................. d-22 d-11 block size encoding .................................................................................... d-23 d-12 option register function summary ............................................................. d-24 d-13 qsm address map ....................................................................................... d-25 d-14 pqspar pin assignments .......................................................................... d-31 d-15 effect of ddrqs on portqs pins ............................................................. d-31 d-16 effect of ddrqs on qsm pin function ....................................................... d-32 d-17 mc68331 module address map ................................................................... d-37 d-18 register bit and field mnemonics ............................................................... d-40
mc68331 introduction motorola user? manual 1-1 1 section 1introduction the mc68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. the mcu is built up from standard modules that interface through a common intermodule bus (imb). standardization facilitates rapid development of devices tailored for specific applica- tions. the mcu incorporates a 32-bit cpu (cpu32), a system integration module (sim), a general-purpose timer (gpt), and a queued serial module (qsm). the mcu can either synthesize an internal clock signal from an external reference or use an external clock input directly. operation with a 32.768-khz reference frequency is standard. because mcu operation is fully static, register and memory contents are not affected by a loss of clock. high-density complementary metal-oxide semiconductor (hcmos) architecture makes the basic power consumption of the mcu low. power consumption can be min- imized by stopping the system clock. the cpu32 instruction set includes a low-power stop (lpstop) command that efficiently implements this capability. documentation for the modular microcontroller family follows the modular construc- tion of the devices in the product line. each microcontroller has a comprehensive us- er's manual that provides sufficient information for normal operation of the device. the user's manual is supplemented by module reference manuals that provide detailed in- formation about module operation and applications. refer to motorola publication ad- vanced microcontroller unit (amcu) literature (br1116/d) for a complete listing of documentation.
motorola introduction mc68331 1-2 user? manual 1
mc68331 nomenclature motorola user? manual 2-1 2 section 2nomenclature the following nomenclature is used throughout the manual. nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 symbols and operators + addition - subtraction or negation (two's complement) * multiplication / division > greater < less = equal 3 equal or greater equal or less 1 not equal and ; inclusive or (or) ? exclusive or (eor) not complementation : concatenation t transferred ? exchanged sign bit; also used to show tolerance sign extension % binary value $ hexadecimal value
motorola nomenclature mc68331 2-2 user? manual 2 2.2 cpu32 registers a6?0 address registers (index registers) a7 (ssp) supervisor stack pointer a7 (usp) user stack pointer ccr condition code register (user portion of sr) d7?0 data registers (index registers) dfc ? alternate function code register pc program counter sfc alternate function code register sr status register vbr vector base register x extend indicator n negative indicator z zero indicator v two's complement overflow indicator c carry/borrow indicator
mc68331 nomenclature motorola user? manual 2-3 2 2.3 pin and signal mnemonics addr[23:0] address bus as address strobe avec autovector berr bus error bg bus grant bgack bus grant acknowledge bkpt breakpoint br bus request clkout system clock cs[10:0] chip selects csboot boot rom chip select data[15:0] data bus ds data strobe dsack[1:0] data and size acknowledge dsclk development serial clock dsi development serial input dso development serial output extal external crystal oscillator connection fc[2:0] function codes freeze freeze halt halt ic[4:1] input capture ifetch instruction fetch ipipe instruction pipeline irq[7:1] interrupt request miso master in slave out modclk clock mode select mosi master out slave in oc[5:1] output compare pai pulse accumulator input pc[6:0] sim i/o port c pclk pulse accumulator clock pcs[3:0] peripheral chip selects pe[7:0] sim i/o port e pf[7:0] sim i/o port f pgp[7:0] gpt i/o port pqs[7:0] qsm i/o port pwma, pwmb pulse width modulator output quot quotient out
motorola nomenclature mc68331 2-4 user? manual 2 r/w read/write reset reset rmc read-modify-write cycle rxd sci receive data sck qspi serial clock siz[1:0] size ss slave select tsc three-state control txd sci transmit data xfc external filter capacitor xtal external crystal oscillator connection
mc68331 nomenclature motorola user? manual 2-5 2 2.4 register mnemonics cforc gpt compare force register creg test control register c cr[0:f] qsm command ram csbarbt chip-select base address register boot rom csbar[0:10] chip-select base address registers [0:10] csorbt chip-select option register boot rom csor[0:10] chip-select option register [0:10] cspar[0:1] chip-select pin assignment registers [0:1] ddre port e data direction register ddrf port f data direction register ddrgp port gp data direction register ddrqs port qs data direction register dreg sim test module distributed register gptmcr gpt module configuration register icr gpt interrupt configuration register oc1d output compare 1 action data register oc1m output compare 1 action mask register pacnt pulse accumulator counter pactl pulse accumulator control register pepar port e pin assignment register pfpar port f pin assignment register picr periodic interrupt control register pitr periodic interrupt timer register portc port c data register porte port e data register portf port f data register portgp port gp data register portqs port qs data register pqspar port qs pin assignment register prescl gpt prescaler register pwma pwm control register a pwmb pwm control register b pwmbufa pwm buffer register a pwmbufb pwm buffer register b pwmc pwm control register c pwmcnt pwm counter qilr qsm interrupt level register qivr qsm interrupt vector register qsmcr qsm configuration register
motorola nomenclature mc68331 2-6 user? manual 2 2.5 conventions logic level one is the voltage that corresponds to a boolean true (1) state. logic level zero is the voltage that corresponds to a boolean false (0) state. set refers specifically to establishing logic level one on a bit or bits. clear refers specifically to establishing logic level zero on a bit or bits. asserted means that a signal is in active logic state. an active low signal changes from logic level one to logic level zero when asserted, and an active high signal chang- es from logic level zero to logic level one. negated means that an asserted signal changes logic state. an active low signal changes from logic level zero to logic level one when negated, and an active high sig- nal changes from logic level one to logic level zero. qtest qsm test register rr[0:f] qsm receive data ram rsr reset status register sccr[0:1] sci control registers [0:1] scdr sci data register scsr sci status register simcr sim module configuration register simtr system integration test register simtre system integration test register (eclk) spcr[0:3] qspi control registers [0:3] spsr qspi status register swsr software watchdog service register syncr clock synthesizer control register sypcr system protection control register tcnt timer counter register tctl[1:2] timer control registers [1:2] tflg[1:2] timer interrupt flag registers [1:2] ti4/o5 timer input capture 4/output compare 5 register tic[1:3] timer input capture registers [1:3] tmsk[1:2] timer interrupt mask register [1:2] toc[1:4] timer output compare registers [1:4] tr[0:f] qsm transmit data ram tstmsra test module master shift register a tstmsrb test module master shift register b tstrc test module repetition count register tstsc test module shift count register
mc68331 nomenclature motorola user? manual 2-7 2 a specific mnemonic within a range is referred to by mnemonic and number. a15 is bit 15 of accumulator a; addr7 is line 7 of the address bus; csor0 is chip-select op- tion register 0. a range of mnemonics is referred to by mnemonic and the numbers that define the range. am[35:30] are bits 35 to 30 of accumulator m; csor[0:5] are the first six option registers. parentheses are used to indicate the content of a register or memory location, rather than the register or memory location itself. (a) is the content of accumulator a. (m : m + 1) is the content of the word at address m. lsb means least significant bit or bits. msb means most significant bit or bits. refer- ences to low and high bytes are spelled out. lsw means least significant word or words. msw means most significant word or words. addr is the address bus. addr[7:0] are the eight lsb of the address bus. data is the data bus. data[15:8] are the eight msb of the data bus.
motorola nomenclature mc68331 2-8 user? manual 2
mc68331 overview motorola user? manual 3-1 3 section 3overview this section contains information about the entire modular microcontroller. it lists the features of each module, shows device functional divisions and pin assignments, sum- marizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. timing and electrical specifications for the entire microcontroller and for individual modules are provided in appendix a electrical characteris- tics . comprehensive module register descriptions and memory maps are provided in appendix d register summary . 3.1 mcu features the following paragraphs highlight capabilities of each of the microcontroller modules. each module is discussed separately in a subsequent section of this user's manual. 3.1.1 system integration module (sim) ?external bus support ?programmable chip-select outputs ?system protection logic ?watchdog timer, clock monitor, and bus monitor ?system protection logic ?pll system clock for low power operation ?background debugging mode 3.1.2 central processing unit (cpu32) ?instruction set supports controller applications ?32-bit architecture ?virtual memory implementation ?loop mode of instruction execution ?table lookup and interpolate instruction ?improved exception handling for controller applications ?trace on change of flow ?hardware breakpoint signal, background mode ?fully static operation 3.1.3 queued serial module (qsm) ?serial communication interface (sci), enhanced universal asynchronous re- ceiver transmitter (uart) with modulus baud rate, parity ?queued serial peripheral interface (spi), high speed bidirectional interface, 80- byte ram, up to 16 automatic transfers ?dual function i/o ports ?continuous cycling, 8 to 16 bits per transfer
motorola overview mc68331 3-2 user? manual 3 3.1.4 general-purpose timer (gpt) ?two 16-bit free-running counters with one nine-stage prescaler ?three input capture channels ?four output compare channels ?one input capture/output compare channel ?one pulse accumulator/event counter input ?two pulse-width modulation outputs ?optional external clock input 3.2 system block diagram and pin assignment diagrams figure 3-1 is a functional diagram of the mcu. although diagram blocks represent the relative size of the physical modules, there is not a one-to-one correspondence be- tween location and size of blocks in the diagram and location and size of integrated- circuit modules. figure 3-2 shows the pin assignments of the 132-pin plastic surface- mount package. figure 3-3 shows the pin assignments of the 144-pin plastic surface- mount package. refer to appendix b mechanical data and ordering in- formation for package dimensions. all pin functions and signal names are shown in this drawing. refer to subsequent paragraphs in this section for pin and signal de- scriptions.
mc68331 overview motorola user? manual 3-3 3 figure 3-1 mcu block diagram 331 block pqs5/pcs2 pqs7/txd pqs4/pcs1 pqs6/pcs3 cpu32 qsm imb gpt pqs0/miso pqs1/mosi pqs2/sck port qs txd pcs2 sck miso mosi control pcs1 pqs3/pcs0/ss pcs0/ss rxd pcs3 bkpt /dsclk ifetch /dsi ipipe /dso dsi dso ipipe ifetch bkpt irq [7:1 ] addr[23:0] control port f port c fc2 fc1 fc0 bg br bgack modclk addr[23:19] clock ebi cs [10:0 ] br /cs0 bg /cs1 bgack /cs2 r/w reset halt berr clkout xtal extal chip selects csboot addr[18:0] data[15:0] data[15:0] quot test freeze/quot tsc control tsc pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pf7/irq7 pf6/irq6 pf5/irq5 pf4/irq4 pf3/irq3 pf2/irq2 pf1/irq1 pf0/modclk control port e siz1 pe7/siz1 siz0 pe6/siz0 dsack0 pe0/dsack0 dsack1 pe1/dsack1 avec pe2/avec pe3/rmc ds pe5/ds rmc pe4/as pwma pwma control as control dsclk freeze port gp pgp7/ic4/oc5/oc1 pgp5/oc3/oc1 pgp2/ic3 pgp0/ic1 pgp1/ic2 control pgp4/oc2/oc1 pgp3/oc1 pwmb pgp6/oc4/oc1 pclk pai pwmb pclk pai pgp7/ic4/oc5/oc1 pgp5/oc3/oc1 pgp2/ic3 pgp0/ic1 pgp1/ic2 pgp4/oc2/oc1 pgp3/oc1 pgp6/oc4/oc1
motorola overview mc68331 3-4 user? manual 3 figure 3-2 pin assignments for 132-pin package 331 132-pin qfp mc68331 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 data9 data10 data11 data12 data13 data14 data15 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 pqs0/miso pqs1/mosi pqs2/sck pqs3/pcs0/ss pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 data0 data1 data2 data3 data4 data5 data6 data7 data8 v dd v ss v dd pe1/dsack1 pe0/dsack0 pe2/avec pe3/rmc pe5/ds csboot bgack /cs2 bg /cs1 br /cs0 51 17 117 16 15 14 13 12 11 10 9 8 7 6 5 4 3 131 130 129 128 127 126 125 124 123 122 121 120 119 118 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 pqs7/txd rxd ipipe /dso freeze/quot xtal extal xfc clkout pf0/modclk pe7/siz1 pe6/siz0 nc pgp0/ic1 pgp1/ic2 pgp2/ic3 pgp3/oc1 pgp4/oc2/oc1 pgp5/oc3/oc1 nc pgp6/oc4/oc1 pgp7/ic4/oc5/oc1 pai nc nc pwma pwmb pclk nc v ss v dd v ss pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pe4/as r/w pf1/irq1 pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset tsc bkpt /dsclk ifetch /dsi 2 1 132 v ddsyn v ss v ss v dd v ss v dd v ss v dd v ss v ss v dd v dd v ss v dd v dd v ss v ss v dd v ss v ss v ss v dd v dd nc
mc68331 overview motorola user? manual 3-5 3 figure 3-3 pin assignments for 144-pin package 3.3 pin descriptions the following tables are a summary of the functional characteristics of mcu pins. ta- ble 3-1 shows types of output drivers. table 3-2 shows all inputs and outputs. digital inputs and outputs use cmos logic levels. an entry in the discrete i/o column indi- cates that a pin can also be used for general-purpose input, output, or both. the i/o port designation is given when it applies. table 3-3 shows characteristics of power pins. refer to figure 3-1 for port organization. 331 144-pin qfp v ss nc fc0/cs3 fc1/cs4 fc2/cs5 addr19/cs6 addr20/cs7 addr21/cs8 addr22/cs9 addr23/cs10 v dd pclk pwmb pwma nc nc nc nc pai pgp6/oc4 v dd v ss nc pgp5/oc3/oc1 pgp4/oc2/oc1 pgp3/oc1 mc68331 nc pe4/as pe6/siz0 pe7/siz1 r/w pf0/modclk pf1/irq1 pf2/irq2 pf3/irq3 pf4/irq4 pf5/irq5 pf6/irq6 pf7/irq7 berr halt reset clkout nc xfc extal v dd xtal freeze/quot tsc bkpt /dsclk ifetch /dsi ipipe /dso rxd pqs7/txd v ss nc pgp2/ic3 pgp1/ic2 pgp0/ic1 nc nc 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 107 108 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 31 32 33 34 35 36 bgack /cs2 bg/cs1 br/cs0 csboot data0 data1 data2 data3 data4 data5 data6 data7 nc data8 nc data9 data10 nc data11 v ss data12 data13 data14 data15 addr0 pe0/dsack0 pe1/dsack1 pe2/avec pe3/rmc pe5/ds v dd nc addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 v dd v ss addr9 addr10 addr11 addr12 nc nc addr13 addr14 addr15 nc addr16 addr17 addr18 pqs0/miso pqs1/mosi pqs2/sck pqs3/pcs0/ss pqs4/pcs1 pqs5/pcs2 pqs6/pcs3 143 144 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 65 68 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 67 69 70 71 72 v ss v dd v ss v dd v ss v dd v dd v ss v ss v dd v ss v ss v dd v dd v ss v dd v ss v ss v dd g p7/ic4/oc5/oc1
motorola overview mc68331 3-6 user? manual 3 table 3-1 mcu driver types type i/o description a o output-only signals that are always driven; no external pull-up required aw o type a output with weak p-channel pull-up during reset b o three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. an external holding resistor is required to maintain logic level while the pin is in the high-impedance state. bo o type b output that can be operated in an open-drain mode table 3-2 mcu pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 /eclk a y n o addr[22:19]/cs[9:6] a y n o pc[6:3] addr[18:0] a y n as b y n i/o pe5 a vec b y n i/o pe2 berr b y n ? ? bg /cs1 b ? ? ? ? bga ck /cs2 b y n ? ? bkpt /dsclk ? y y ? ? br /cs0 b y n ? clkout a ? ? ? ? csboo t b ? ? ? ? data[15:0]1 aw y n ? ? ds b y n i/o pe4 dsa ck1 b y n i/o pe1 dsa ck0 b y n i/o pe0 dsi/ifetch a y y ? dso/ipipe a ? extal2 ? ? special ? ? fc[2:0]/cs[5:3] a y n o pc[2:0] freeze/quot a ? ? ? ? ic4/oc5 a y y i/o gp4 ic[3:1] a y y i/o gp[7:5] hal t bo y n ? ? irq[7:1] b y y i/o pf[7:1] miso bo y y i/o pqs0 modclk 1 b y n i/o pf0 mosi bo y y i/o pqs1 oc[4:1] a y y i/o gp[3:0] pai 2 ? y y i ? pclk 2 ? y y i ? pcso /ss bo y y i/o pqs3 pcs[3:1] bo y y i/o pqs[6:4] pwma, pwmb a ? ? o ? r/w a y n ? ? reset bo y y ? ? rmc b y n i/o pe3
mc68331 overview motorola user? manual 3-7 3 3.4 signal descriptions the following tables define mcu signals. table 3-4 shows signal origin, type, and ac- tive state. table 3-5 describes signal functions. both tables are sorted alphabetically by mnemonic. mcu pins often have multiple functions. more than one description can apply to a pin. 1. data[15:0] are synchronized during reset only. modclk is synchronized only when used as an input port pin. 2. extal, xfc, and xtal are clock reference connections. 3. pai and pclk can be used for discrete input, but are not part of an i/o port. rxd ? n n ? ? sck bo y y i/o pqs2 siz[1:0] b y n i/o pe[7:6] tsc ? y y ? ? txd bo y y i/o pqs7 xfc 3 ? ? ? special ? xtal 3 ? ? ? special ? table 3-3 mcu power connections pin mnemonic description v ddsyn clock synthesizer power v sse /v dde external periphery power (source and drain) v ss i/v ddi internal module power (source and drain) table 3-4 signal characteristics signal name mcu module signal type active state addr[23:0] sim bus ? as sim output 0 a vec sim input 0 berr sim input 0 bg sim output 0 bga ck sim input 0 bkpt cpu32 input 0 br sim input 0 clkout sim output ? cs[10:0] sim output 0 csboo t sim output 0 data[15:0] sim bus ? ds sim output 0 dsa ck[1:0] sim input 0 dsclk cpu32 input serial clock dsi cpu32 input (serial data) dso cpu32 output (serial data) extal sim input ? table 3-2 mcu pin characteristics (continued) pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation
motorola overview mc68331 3-8 user? manual 3 fc[2:0] sim output ? freeze sim output 1 hal t sim input/output 0 ic[4:1] gpt input ? ifetch cpu32 output ? ipipe cpu32 output ? irq[7:1] sim input 0 miso qsm input/output ? modclk sim input ? mosi qsm input/output ? oc[5:1] gpt output ? pai gpt input ? pc[6:0] sim output (port) pcs[3:0] qsm input/output pe[7:0] sim input/output (port) pf[7:0] sim input/output (port) pgp[7:0] gpt input/output (port) pqs[7:0] qsm input/output (port) pclk gpt input ? pwma, pwmb gpt output ? quot sim output ? reset sim input/output 0 rmc sim output 0 r/w sim output 1/0 rxd qsm input ? sck qsm input/output ? siz[1:0] sim output ? ss qsm input 0 tsc sim input ? txd qsm output ? xfc sim input ? xtal sim output ? table 3-5 signal function signal name mnemonic function address bus addr[23:0] 24-bit address bus address strobe as indicates that a valid address is on the address bus autovector a vec requests an automatic vector during interrupt acknowledge bus error berr indicates that a bus error has occurred bus grant bg indicates that the mcu has relinquished the bus bus grant acknowledge bga ck indicates that an external device has assumed bus mastership breakpoint bkpt signals a hardware breakpoint to the cpu bus request br indicates that an external device requires bus mastership system clockout clkout system clock output chip selects cs[10:0] select external devices at programmed addresses boot chip select csboo t chip select for external boot start-up rom data bus data[15:0] 16-bit data bus table 3-4 signal characteristics (continued) signal name mcu module signal type active state
mc68331 overview motorola user? manual 3-9 3 data strobe ds during a read cycle, indicates when it is possible for an external device to place data on the data bus. during a write cycle, indicates that valid data is on the data bus. data and size acknowledge dsa ck[1:0] provide asynchronous data transfers and dynamic bus sizing development serial in, out, clock dsi, dso, dsclk serial i/o and clock for background debugging mode crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used function codes fc[2:0] identify processor state and current address space freeze freeze indicates that the cpu has entered background mode halt hal t suspend external bus activity input capture ic[3:1] when a specified transition is detected on an input capture pin, the value in an internal gpt counter is latched input capture 4/ output compare 5 ic4/oc5 can be configured for either an input capture or output compare instruction pipeline ipipe , ifetch indicate instruction pipeline activity interrupt request level irq[7:1] provides an interrupt priority level to the cpu master in slave out miso serial input to qspi in master mode; serial output from qspi in slave mode clock mode select modclk selects the source and type of system clock master out slave in mosi serial output from qspi in master mode; serial input to qspi in slave mode output compare oc[5:1] change state when the value of an internal gpt counter matches a value stored in a gpt control register pulse accumulator input pai signal input to the pulse accumulator port c pc[6:0] sim digital output port signals auxiliary timer clock input pclk external clock dedicated to the gpt peripheral chip select pcs[3:0] qspi peripheral chip selects port e pe[7:0] sim digital i/o port signals port f pf[7:0] sim digital i/o port signals port gp pgp[7:0] gpt digital i/o port signals port qs pqs[7:0] qsm digital i/o port signals pulse-width modulation pwma, pwmb output for pwm quotient out quot provides the quotient bit of the polynomial divider reset reset system reset read-modify-write cycle rmc indicates an indivisible read-modify-write instruction read/write r/w indicates the direction of data transfer on the bus sci receive data rxd serial input to the sci qspi serial clock sck clock output from qspi in master mode; clock input to qspi in slave mode size siz[1:0] indicates the number of bytes to be transferred during a bus cycle slave select ss causes serial transmission when qspi is in slave mode; causes mode fault in master mode three-state control tsc places all output drivers in a high-impedance state sci transmit data txd serial output from the sci external filter capacitor xfc connection for external phase-locked loop filter capacitor table 3-5 signal function (continued) signal name mnemonic function
motorola overview mc68331 3-10 user? manual 3 3.5 intermodule bus the intermodule bus (imb) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. it contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored inter- rupts. the standardized modules in the mcu communicate with one another and with external components through the imb. the imb in the mcu uses 24 address and 16 data lines. 3.6 system memory map figure 3-4 , figure 3-5 , figure 3-6 , figure 3-7 , and figure 3-8 are mcu memory maps. figure 3-4 shows imb addresses of internal registers. figure 3-5 through fig- ure 3-8 show system memory maps that use different external decoding schemes. 3.6.1 internal register map in figure 3-4 , imb addr[23:20] are represented by the letter y. the value represent- ed by y determines the base address of mcu module control registers. in m68300 mi- crocontrollers, y is equal to m111, where m is the logic state of the module mapping (mm) bit in the system integration module configuration register (simcr). 3.6.2 address space maps figure 3-5 shows a single memory space. function codes fc[2:0] are not decoded externally so that separate user/supervisor or program/data spaces are not provided. in figure 3-6 , fc2 is decoded, resulting in separate supervisor and user spaces. fc[1:0] are not decoded, so that separate program and data spaces are not provided. in figure 3-7 and figure 3-8 , fc[2:0] are decoded, resulting in four separate memory spaces: supervisor/program, supervisor/data, user/program and user/data. all exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. only the initial reset vector is fixed in the processor's memory map. once initialization is complete, there are no fixed as- signments. since the vector base register (vbr) provides the base address of the vec- tor table, the vector table can be located anywhere in memory. refer to section 5 central processing unit for more information concerning memory manage- ment, extended addressing, and exception processing. refer to section 4 system integration module for more information concerning function codes and ad- dress space types.
mc68331 overview motorola user? manual 3-11 3 figure 3-4 internal register memory map 331 address map sim reserved qsm $yffa00 $yff000 $yff93f $yff900 $yfffff $yffc00 $yffdff $yffaff $yffa80 $yffa7f gpt y = m111, where m is the state of the module mapping (mm) bit in the sim configuration register.
motorola overview mc68331 3-12 user? manual 3 figure 3-5 overall memory map 331 s/u comb map internal registers (mm = 1) $ 000000 $ffffff $ff0000 combined supervisor and user space $7ff000 internal registers (mm = 0) notes: 1. location of the exception vector table is determined by the vector base register. the vector address is the sum of the vector base register and the vector offset. 2. location of the module control registers is determined by the state of the module mapping (mm) bit in the sim configuration register. y = m111, where m is the state of the mm bit. 3. unused addresses within the internal register block are mapped externally. "reserved" blocks are not mapped externally. $xx03fc $xx0000 reset ?initial stack pointer reset ?initial pc bus error address error illegal instruction zero division chk, chk2 instructions trapcc, trapv instructions privilege violation trace line 1010 emulator line 1111 emulator hardware breakpoint (reserved coprocessor protocol violation) format error and uninitialized interrupt format error and uninitialized interrupt (unassigned, reserved) spurious interrupt level 1 interrupt autovector level 2 interrupt autovector level 3 interrupt autovector level 4 interrupt autovector level 5 interrupt autovector level 6 interrupt autovector level 7 interrupt autovector tap instruction vectors (0?5) (reserved, coprocessor) (unassigned, reserved) user-defined vectors 0000 0004 0008 000c 0010 0014 0018 001c 0020 0024 0028 002c 0030 0034 0038 003c 0040?05c 006c 0064 0068 006c 0070 0074 0078 007c 0080?0bc 00c0?0eb 00ec?0fc 0100?3fc vector offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16?3 24 25 26 27 28 29 30 31 32?7 48?8 59?3 64?55 vector number type of exception $yff000 $yff93f gpt $yffa00 reserved $yffaff $yffa7f sim $yffa80 reserved $yffc00 $yfffff qsm $yff900 $yffdff
mc68331 overview motorola user? manual 3-13 3 figure 3-6 separate supervisor and user space map 331 s/u sep map internal registers $000000 $ffffff $ff0000 supervisor space $7ff000 internal registers notes: 1. location of the exception vector table is determined by the vector base register. the vector address is the sum of the vector base register and the vector offset. 2. location of the module control registers is determined by the state of the module mapping (mm) bit in the sim configuration register. y = m111, where m is the state of the mm bit. 3. unused addresses within the internal register block are mapped externally. "reserved" blocks are not mapped externally. $xx03fc $xx0000 reset ?initial stack pointer reset ?initial pc bus error address error illegal instruction zero division chk, chk2 instructions trapcc, trapv instructions privilege violation trace line 1010 emulator line 1111 emulator hardware breakpoint (reserved coprocessor protocol violation) format error and uninitialized interrupt format error and uninitialized interrupt (unassigned, reserved) spurious interrupt level 1 interrupt autovector level 2 interrupt autovector level 3 interrupt autovector level 4 interrupt autovector level 5 interrupt autovector level 6 interrupt autovector level 7 interrupt autovector tap instruction vectors (0?5) (reserved, coprocessor) (unassigned, reserved) user-defined vectors 0000 0004 0008 000c 0010 0014 0018 001c 0020 0024 0028 002c 0030 0034 0038 003c 0040?05c 006c 0064 0068 006c 0070 0074 0078 007c 0080?0bc 00c0?0eb 00ec?0fc 0100?3fc vector offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16?3 24 25 26 27 28 29 30 31 32?7 48?8 59?3 64?55 vector number type of exception internal registers internal registers user space $000000 $7ff000 4 $ff0000 4 $ffffff 4. some internal registers are not available in user space. $yff000 $yff93f gpt $yffa00 reserved $yffaff $yffa7f sim $yffa80 reserved $yffc00 $yfffff qsm $yff900 $yffdff
motorola overview mc68331 3-14 user? manual 3 figure 3-7 supervisor space (separate program/data space) map 331 super p/d map internal registers $000000 $ffffff $ff0000 $7ff000 internal registers notes: 1. location of the exception vector table is determined by the vector base register. the vector address is the sum of the vector base register and the vector offset. 2. location of the module control registers is determined by the state of the module mapping (mm) bit in the sim configuration register. y = m111, where m is the state of the mm bit. 3. unused addresses within the internal register block are mapped externally. "reserved" blocks are not mapped externally. $xx03fc $xx0000 reset ?initial stack pointer reset ?initial pc bus error address error illegal instruction zero division chk, chk2 instructions trapcc, trapv instructions privilege violation trace line 1010 emulator line 1111 emulator hardware breakpoint (reserved coprocessor protocol violation) format error and uninitialized interrupt format error and uninitialized interrupt (unassigned, reserved) spurious interrupt level 1 interrupt autovector level 2 interrupt autovector level 3 interrupt autovector level 4 interrupt autovector level 5 interrupt autovector level 6 interrupt autovector level 7 interrupt autovector tap instruction vectors (0?5) (reserved, coprocessor) (unassigned, reserved) user-defined vectors 0000 0004 0008 000c 0010 0014 0018 001c 0020 0024 0028 002c 0030 0034 0038 003c 0040?05c 006c 0064 0068 006c 0070 0074 0078 007c 0080?0bc 00c0?0eb 00ec?0fc 0100?3fc vector offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16?3 24 25 26 27 28 29 30 31 32?7 48?8 59?3 64?55 vector number $000000 $ffffff 4. some internal registers are not available in user space. $xx0004 $xx0000 reset ?initial stack pointer reset ?initial pc 0000 0004 vector offset 0 1 vector number exception vectors located in supervisor program space exception vectors located in supervisor data space supervisor data space supervisor program space $yff000 $yff93f gpt $yffa00 reserved $yffaff $yffa7f sim $yffa80 reserved $yffc00 $yfffff qsm $yff900 $yffdff
mc68331 overview motorola user? manual 3-15 3 figure 3-8 user space (separate program/data space) map 331 user p/d map internal registers $000000 $ffffff $ff0000 $7ff000 internal registers notes: 1. location of the module control registers is determined by the state of the module mapping (mm) bit in the sim configuration register. y = m111, where m is the state of the mm bit. 2. unused addresses within the internal register block are mapped externally. "reserved" blocks are not mapped externally. 3. some internal registers are not available in user space. $000000 $ffffff user data space user program space $yff000 $yff93f gpt $yffa00 reserved $yffaff $yffa7f sim $yffa80 reserved $yffc00 $yfffff qsm $yff900 $yffdff
motorola overview mc68331 3-16 user? manual 3 3.7 system reset the following information is a concise reference only. system reset is a complex op- eration. to understand operation during and after reset, refer to section 4 system integration module , paragraph 4.6 reset for a more complete discussion of the reset function. 3.7.1 sim reset mode selection the logic states of certain data bus pins during reset determine sim operating config- uration. in addition, the state of the modclk pin determines system clock source and the state of the bkpt pin determines what happens during subsequent breakpoint as- sertions. table 3-6 is a summary of reset mode selection options. table 3-6 sim reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboo t 16-bit csboo t 8-bit data1 cs0 cs1 cs2 brbg bga ck data2 cs3 cs4 cs5 fc0fc1fc2 data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] data8 dsa ck0 , dsa ck1 , a vec , ds , as , siz[1:0] porte data9 irq[7:1] , modclk portf data11 test mode disabled test mode enabled modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled
mc68331 overview motorola user? manual 3-17 3 3.7.2 mcu module pin function during reset generally, pins associated with modules other than the sim default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. refer to individual module sections in this manual for more infor- mation. table 3-7 is a summary of module pin function out of reset. table 3-7 module pin functions module pin mnemonic function cpu32 dsi/ifetch dsi/ifetch dso/ipipe dso/ipipe bkpt /dsclk bkpt /dsclk gpt pgp7/ic4/oc5 discrete input pgp[6:3]/oc[4:1] discrete input pgp[2:0]/ic[3:1] discrete input pai discrete input pclk discrete input pwma, pwmb discrete output qsm pqs7/txd discrete input pqs[6:4]/pcs[3:1] discrete input pqs3/pcs0/ss discrete input pqs2/sck discrete input pqs1/mosi discrete input pqs0/miso discrete input rxd rxd
motorola overview mc68331 3-18 user? manual 3
mc68331 system integration module motorola user? manual 4-1 4 section 4 system integration module this section is an overview of sim function. refer to the sim reference manual (sim- rm/ad) for a comprehensive discussion of sim capabilities. refer to appendix d register summary for information concerning the sim address map and register structure. 4.1 general the system integration module (sim) consists of five functional blocks. figure 4-1 is a block diagram of the sim. the system configuration and protection block controls configuration parameters and provides bus and software watchdog monitors. in addition, it provides a periodic inter- rupt generator to support execution of time-critical control routines. the system clock generates clock signals used by the sim, other imb modules, and external devices. the external bus interface handles the transfer of information between imb modules and external address space. ebi pins can also be configured for use as general-pur- pose i/o ports e and f. the chip-select block provides 12 chip-select signals. each chip-select signal has an associated base register and option register that contain the programmable character- istics of that chip select. chip-select pins can also be configured for use as general- purpose output port c. the system test block incorporates hardware necessary for testing the mcu. it is used to perform factory tests, and its use in normal applications is not supported.
motorola system integration module mc68331 4-2 user? manual 4 figure 4-1 system integration module block diagram 4.2 system configuration and protection the system configuration and protection functional block controls module configura- tion, preserves reset status, monitors internal activity, and provides periodic interrupt generation. figure 4-2 is a block diagram of the submodule. s(c)im block system configuration and protection clock synthesizer chip selects external bus interface factory test clkout extal modclk chip selects external bus reset tsc freeze/quot
mc68331 system integration module motorola user? manual 4-3 4 figure 4-2 system configuration and protection 4.2.1 module mapping control registers for all the modules in the microcontroller are mapped into a 4-kbyte block. the state of the module mapping bit (mm) in the sim module configuration reg- ister (simcr) determines where the control register block is located in the system memory map. when mm = 0, register addresses range from $7ff000 to $7fffff; when mm = 1, register addresses range from $fff000 to $ffffff. 4.2.2 interrupt arbitration each module that can generate interrupt requests has an interrupt arbitration (iarb) field. arbitration between interrupt requests of the same priority is performed by serial contention between iarb field bit values. contention must take place whenever an in- terrupt request is acknowledged, even when there is only a single request pending. for an interrupt to be serviced, the appropriate iarb field must have a non-zero value. if an interrupt request from a module with an iarb field value of %0000 is recognized, the cpu32 processes a spurious interrupt exception. sys protect block module configuration and test reset status halt monitor bus monitor spurious interrupt monitor software watchdog timer periodic interrupt timer prescaler clock berr reset request reset request 2 9 irq [7:1 ]
motorola system integration module mc68331 4-4 user? manual 4 because the sim routes external interrupt requests to the cpu32, the sim iarb field value is used for arbitration between internal and external interrupts of the same pri- ority. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000, which prevents sim interrupts from being discarded during initialization. refer to 4.7 interrupts for a discussion of interrupt arbitration. 4.2.3 show internal cycles a show cycle allows internal bus transfers to be monitored externally. the shen field in the simcr determines what the external bus interface does during internal transfer operations. table 4-1 shows whether data is driven externally, and whether external bus arbitration can occur. refer to 4.5.6.2 show cycles for more information. 4.2.4 factory test mode the internal imb can serve as slave to an external master for direct module testing. this test mode is reserved for factory test. slave mode is enabled by holding data11 low during reset. the slave enabled (slven) bit is a read-only bit that shows the reset state of data11. 4.2.5 register access the cpu32 can operate at either of two privilege levels. supervisor level is more priv- ileged than user level ?all instructions and system resources are available at super- visor level, but access is restricted at user level. effective use of privilege level can protect system resources from uncontrolled access. the state of the s bit in the cpu status register determines access level, and whether the user or supervisor stack pointer is used for stacking operations. the supv bit places sim global registers in either supervisor or user data space. when supv = 0, registers with controlled access are accessible from either the user or supervisor privilege level; when supv = 1, reg- isters with controlled access are restricted to supervisor access only. 4.2.6 reset status the reset status register (rsr) latches internal mcu status during reset. refer to 4.6.9 reset status register for more information. 4.2.7 bus monitor the internal bus monitor checks data and size acknowledge (dsack ) or autovector (avec ) signal response times during normal bus cycles. the monitor asserts the in- ternal bus error (berr ) signal when the response time is excessively long. table 4-1 show cycle enable bits shen action 00 show cycles disabled, external arbitration enabled 01 show cycles enabled, external arbitration disabled 10 show cycles enabled, external arbitration enabled 11 show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant
mc68331 system integration module motorola user? manual 4-5 4 dsack and avec response times are measured in clock cycles. maximum allowable response time can be selected by setting the bus monitor timing (bmt) field in the sys- tem protection control register (sypcr). table 4-2 shows the periods allowed. the monitor does not check dsack response on the external bus unless the cpu32 initiates a bus cycle. the bme bit in sypcr enables the internal bus monitor for inter- nal to external bus cycles. if a system contains external bus masters, an external bus monitor must be implemented and the internal-to-external bus monitor option must be disabled. when monitoring transfers to an 8-bit port, the bus monitor does not reset until both byte accesses of a word transfer are completed. monitor time-out period must be at least twice the number of clocks that a single byte access requires. 4.2.8 halt monitor the halt monitor responds to an assertion of the halt signal on the internal bus. refer to 4.5.5.2 double bus faults for more information. halt monitor reset can be inhibited by the halt monitor (hme) bit in sypcr. 4.2.9 spurious interrupt monitor during interrupt exception processing, the cpu32 normally acknowledges an interrupt request, recognizes the highest priority source, and then acquires a vector or re- sponds to a request for autovectoring. the spurious interrupt monitor asserts the in- ternal bus error signal (berr ) if no interrupt arbitration occurs during interrupt exception processing. the assertion of berr causes the cpu32 to load the spurious interrupt exception vector into the program counter. the spurious interrupt monitor cannot be disabled. refer to 4.7 interrupts for further information. for detailed infor- mation about interrupt exception processing, refer to section 5 central pro- cessing unit . 4.2.10 software watchdog the software watchdog is controlled by the software watchdog enable (swe) bit in sypcr. when enabled, the watchdog requires that a service sequence be written to software service register swsr on a periodic basis. if servicing does not take place, the watchdog times out and asserts the reset signal. perform a software watchdog service sequence as follows: 1. write $55 to swsr. 2. write $aa to swsr. table 4-2 bus monitor period bmt bus monitor time-out period 00 64 system clocks 01 32 system clocks 10 16 system clocks 11 8 system clocks
motorola system integration module mc68331 4-6 user? manual 4 both writes must occur before time-out in the order listed, but any number of instruc- tions can be executed between the two writes. watchdog clock rate is affected by the software watchdog prescale (swp) and soft- ware watchdog timing (swt) fields in sypcr. swp determines system clock prescaling for the watchdog timer and determines that one of two options, either no prescaling or prescaling by a factor of 512, can be select- ed. the value of swp is affected by the state of the modclk pin during reset, as shown in table 4-3 . system software can change swp value. the swt field selects the divide ratio used to establish software watchdog time-out period. time-out period is given by the following equations. or table 4-4 shows the ratio for each combination of swp and swt bits. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time- out period can take effect. figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe- riodic interrupt timer. table 4-3 modclk pin and swp bit during reset modclk swp 0 (external clock) 1 ( ? 512) 1 (internal clock) 0 ( ? 1) table 4-4 software watchdog ratio swp swt ratio 000 2 9 001 2 11 010 2 13 011 2 15 100 2 18 101 2 20 110 2 22 111 2 24 time-out period 1 extal frequency divide ratio ------------------------------------------------------------------------------------ - = time-out period divide ratio extal frequency ------------------------------------------------ - =
mc68331 system integration module motorola user? manual 4-7 4 figure 4-3 periodic interrupt timer and software watchdog timer 4.2.11 periodic interrupt timer the periodic interrupt timer allows the generation of interrupts of specific priority at pre- determined intervals. this capability is often used to schedule control system tasks that must be performed within time constraints. the timer consists of a prescaler, a modulus counter, and registers that determine interrupt timing, priority and vector as- signment. refer to section 5 central processing unit for further information about interrupt exception processing. the periodic interrupt modulus counter is clocked by a signal derived from the buffered crystal oscillator (extal) input pin unless an external frequency source is used. the value of the periodic timer prescaler (ptp) bit in the periodic interrupt timer register (pitr) determines system clock prescaling for the watchdog timer. one of two op- tions, either no prescaling, or prescaling by a factor of 512, can be selected. the value of ptp is affected by the state of the modclk pin during reset, as shown in table 4- 5 . system software can change ptp value. either clock signal (extal or extal ? 512) is divided by four before driving the mod- ulus counter (pitclk). the modulus counter is initialized by writing a value to the pe- riodic timer modulus timer modulus (pitm) field in the pitr. a zero value turns off the periodic timer. when the modulus counter value reaches zero, an interrupt is generat- ed. the modulus counter is then reloaded with the value in pitm and counting repeats. if a new value is written to pitr, it is loaded into the modulus counter when the current count is completed. table 4-5 modclk pin and ptp bit at reset modclk ptp 0 (external clock) 1 ( ? 512) 1 (internal clock) 0 ( ? 1) clock disable prescaler (2 9 ) clock mux extal lpstop swp ptp freeze swclk pitclk preclk 2 9 ? 4 reset pit interrupt pitr swt1 swt0 swe 15 stage divider chain (2 15 ) 2 11 2 13 2 15 8-bit modulus pit block counter
motorola system integration module mc68331 4-8 user? manual 4 use the following expression to calculate timer period. interrupt priority and vectoring are determined by the values of the periodic interrupt request level (pirql) and periodic interrupt vector (piv) fields in the periodic interrupt control register (picr). content of pirql is compared to the cpu32 interrupt priority mask to determine whether the interrupt is recognized. table 4-6 shows priority of pirql values. be- cause of sim hardware prioritization, a pit interrupt is serviced before an external in- terrupt request of the same priority. the periodic timer continues to run when the interrupt is disabled. the piv field contains the periodic interrupt vector. the vector is placed on the imb when an interrupt request is made. the vector number used to calculate the address of the appropriate exception vector in the exception vector table. reset value of the piv field is $0f, which corresponds to the uninitialized interrupt exception vector. 4.2.12 low-power stop operation when the cpu32 executes the lpstop instruction, the current interrupt priority mask is stored in the clock control logic, internal clocks are disabled according to the state of the stsim bit in the simcr, and the mcu enters low-power stop mode. the bus monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power stop. during low-power stop, the clock input to the software watchdog timer is disabled and the timer stops. the software watchdog begins to run again on the first rising clock edge after low-power stop ends. the watchdog is not reset by low-power stop. a ser- vice sequence must be performed to reset the timer. the periodic interrupt timer does not respond to the lpstop instruction, but continues to run during lpstop. to stop the periodic interrupt timer, pitr must be loaded with a zero value before the lpstop instruction is executed. a pit interrupt, or an external interrupt request, can bring the mcu out of the low-power stop condition if it has a higher priority than the interrupt mask value stored in the clock control logic when low- power stop is initiated. lpstop can be terminated by a reset. table 4-6 periodic interrupt priority pirql priority level 000 periodic interrupt disabled 001 interrupt priority level 1 010 interrupt priority level 2 011 interrupt priority level 3 100 interrupt priority level 4 101 interrupt priority level 5 110 interrupt priority level 6 111 interrupt priority level 7 pit period pit modulus () prescaler value () 4 () extal frequency ---------------------------------------------------------------------------------------------- =
mc68331 system integration module motorola user? manual 4-9 4 4.2.13 freeze operation the freeze signal halts mcu operations during debugging. freeze is asserted in- ternally by the cpu32 if a breakpoint occurs while background mode is enabled. when freeze is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected. the halt monitor and spurious interrupt monitor continue to operate normally. setting the freeze bus monitor (frzbm) bit in the simcr disables the bus monitor when freeze is asserted, and setting the freeze software watchdog (frzsw) bit disables the software watchdog and the periodic interrupt timer when freeze is asserted. when frzsw is set, freeze assertion must be at least two times the pit clock source period to ensure an accurate number of pit counts. 4.3 system clock the system clock in the sim provides timing signals for the imb modules and for an external peripheral bus. because the mcu is a fully static design, register and memory contents are not affected when the clock rate changes. system hardware and software support changes in clock rate during operation. the system clock signal can be generated in one of three ways. an internal phase- locked loop can synthesize the clock from either an internal reference or an external reference, or the clock signal can be input from an external frequency source. keep these clock sources in mind while reading the rest of this section. figure 4-4 is a block diagram of the system clock. refer to appendix a electrical characteris- tics for clock specifications. figure 4-4 system clock block diagram 32 pll block clkout phase comparator low-pass filter vco crystal oscillator system clock system clock control feedback divider w x y extal xtal xfc v ddsyn
motorola system integration module mc68331 4-10 user? manual 4 4.3.1 clock sources the state of the clock mode (modclk) pin during reset determines clock source. when modclk is held high during reset, the clock synthesizer generates a clock sig- nal from either an internal or an external reference frequency ?the clock synthesizer control register (syncr) determines operating frequency and mode of operation. when modclk is held low during reset, the clock synthesizer is disabled and an ex- ternal system clock signal must be applied ?syncr control bits have no effect. to generate a reference frequency using the internal oscillator a reference crystal must be connected between the extal and xtal pins. figure 4-5 shows a recom- mended circuit. figure 4-5 system clock oscillator circuit if an external reference signal or an external system clock signal is applied via the ex- tal pin, the xtal pin must be left floating. external reference signal frequency must be less than or equal to maximum specified reference frequency. external system clock signal frequency must be less than or equal to maximum specified system clock frequency. when an external system clock signal is applied (pll disabled, modclk = 0 during reset), the duty cycle of the input is critical, especially at operating frequencies close to maximum. the relationship between clock signal duty cycle and clock signal period is expressed: 4.3.2 clock synthesizer operation v ddsyn is used to power the clock circuits when either an internal or an external ref- erence frequency is applied. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. a quiet power sup- ply must be used as the v ddsyn source. adequate external bypass capacitors should be placed as close as possible to the v ddsyn pin to assure stable operating frequen- v ssi extal xtal 22 pf * c1 330k r1 32 oscillator resistance and capacitance based on a test circuit constructed with a daishinku dmx-38 32.768-khz crystal. specific components must be based on crystal type. contact crystal vendor for exact circuit. * 22 pf * c2 10m r2 minumum external clock period minimum external clock high low time 50% percentage variation of external clock input duty cycle ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- =
mc68331 system integration module motorola user? manual 4-11 4 cy. when an external system clock signal is applied and the pll is disabled, v ddsyn should be connected to the v dd supply. refer to the sim reference manual (simrm/ ad) for more information regarding system clock power supply conditioning. a voltage controlled oscillator (vco) generates the system clock signal. to maintain a 50% clock duty cycle, vco frequency is either two or four times system clock fre- quency, depending on the state of the x bit in syncr. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is a reference signal, either from the crystal oscillator or from an external source. the comparator generates a control signal proportional to the difference in phase between the two inputs. the signal is low- pass filtered and used to correct vco output frequency. filter geometry can vary, depending upon the external environment and required clock stability. figure 4-6 shows two recommended filters. xfc pin leakage must be as specified in appendix a electrical characteristics to maintain optimum stability and pll performance. an external filter network connected to the xfc pin is not required when an external system clock signal is applied and the pll is disabled. the xfc pin must be left float- ing in this case. figure 4-6 system clock filter networks the synthesizer locks when vco frequency is equal to extal frequency. lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. whenever comparator input changes, the synthesizer must relock. lock status is shown by the slock bit in syncr. during power-up, the mcu does not come out of reset state until the synthesizer locks. crystal type, characteristic fre- quency, and layout of external oscillator circuitry affect lock time. when the clock synthesizer is used, control register syncr determines operating fre- quency and various modes of operation. the syncr w bit controls a three-bit pres- caler in the feedback divider. setting w increases vco speed by a factor of four. the 16/32 xfc conn 1. maintain low-leakage on the xfc node. see appendix a electrical characteristics for more information. 2. recommended loop filter for reduced sensitivity to low-frequency noise. 0.01 m f 0.1 m f normal operating environment high-stability operating environment c4 c1 v ssi v ddsyn xfc 1 0.1 m f c3 0.01 m f 0.1 m f c4 c1 v ssi v ddsyn xfc 1, 2 0.1 m f c3 0.01 m f c2 18k w r1
motorola system integration module mc68331 4-12 user? manual 4 syncr y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of y + 1. when w or y values change, vco frequency changes, and there is a vco relock delay. the syncr x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x = 0 (reset state), the divider is en- abled, and system clock frequency is one-fourth vco frequency; setting x disables the divider, doubling clock speed without changing vco speed. there is no relock de- lay when clock speed is changed by the x bit. clock frequency is determined by syncr bit settings as follows: the reset state of syncr ($3f00) produces a modulus-64 count. for the device to perform correctly, system clock and vco frequencies selected by the w, x, and y bits must be within the limits specified for the mcu. do not use a com- bination of bit values that selects either an operating frequency or a vco frequency greater than the maximum specified values in appendix a electrical charac- teristics . table 4-7 shows clock control multipliers for all possible combinations of syncr bits. table 4-8 shows clock frequencies available with a 32.768-khz reference and a max- imum specified clock frequency of 20.97 mhz. table 4-7 clock control multipliers to obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. modulus prescalers y [w:x] = 00 [w:x] = 01 [w:x] = 10 [w:x] = 11 000000 4 8 16 32 000001 8 16 32 64 000010 12 24 48 96 011111 16 32 64 128 000011 20 40 80 160 000100 24 48 96 192 000101 28 56 112 224 000110 32 64 128 256 000111 36 72 144 288 001000 40 80 160 320 001001 44 88 176 352 001010 48 96 192 384 001011 52 104 208 416 001100 56 112 224 448 001101 60 120 240 480 001110 64 128 256 512 001111 68 136 272 544 010000 72 144 288 576 010001 76 152 304 608 010010 80 160 320 640 010011 84 168 336 672 f system f reference 4y 1 + () 2 2w x + ()] [ =
mc68331 system integration module motorola user? manual 4-13 4 010100 88 176 352 704 010101 92 184 368 736 010110 96 192 384 768 010111 100 200 400 800 011000 104 208 416 832 011001 108 216 432 864 011010 112 224 448 896 011011 116 232 464 928 011100 120 240 480 960 011101 124 248 496 992 011110 128 256 512 1024 100000 132 264 528 1056 100001 136 272 544 1088 100010 140 280 560 1120 100011 144 288 576 1152 100100 148 296 592 1184 100101 152 304 608 1216 100110 156 312 624 1248 100111 160 320 640 1280 101000 164 328 656 1312 101001 168 336 672 1344 101010 172 344 688 1376 101011 176 352 704 1408 101100 180 360 720 1440 101101 184 368 736 1472 101110 188 376 752 1504 101111 192 384 768 1536 110000 196 392 784 1568 110001 200 400 800 1600 110010 204 408 816 1632 110011 208 416 832 1664 110100 212 424 848 1696 110101 216 432 864 1728 110110 220 440 880 1760 110111 224 448 896 1792 111000 228 456 912 1824 111001 232 464 928 1856 111010 236 472 944 1888 111011 240 480 960 1920 111100 244 488 976 1952 111101 248 496 992 1984 111110 252 504 1008 2016 111111 256 512 1024 2048 table 4-7 clock control multipliers (continued) to obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. modulus prescalers y [w:x] = 00 [w:x] = 01 [w:x] = 10 [w:x] = 11
motorola system integration module mc68331 4-14 user? manual 4 table 4-8 system frequencies from 32.768-khz reference to obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell. shaded cells contain values that exceed specified maximum system frequency. modulus prescaler y [w:x] = 00 [w:x] = 01 [w:x] = 10 [w:x] = 11 000000 131 262 524 1049 000001 262 524 1049 2097 000010 393 786 1573 3146 000011 524 1049 2097 4194 000100 655 1311 2621 5243 000101 786 1573 3146 6291 000110 918 1835 3670 7340 000111 1049 2097 4194 8389 001000 1180 2359 4719 9437 001001 1311 2621 5243 10486 001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 17826 010001 2359 4719 9437 18874 010010 2490 4981 9961 19923 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 010101 2884 5767 11534 23069 010110 3015 6029 12059 24117 010111 3146 6291 12583 25166 011000 3277 6554 13107 26214 011001 3408 6816 13631 27263 011010 3539 7078 14156 28312 011011 3670 7340 14680 29360 011100 3801 7602 15204 30409 011101 3932 7864 15729 31457 011110 4063 8126 16253 32506 011111 4194 8389 16777 33554 100000 4325 8651 17302 34603 100001 4456 8913 17826 35652 100010 4588 9175 18350 36700 100011 4719 9437 18874 37749 100100 4850 9699 19399 38797 100101 4981 9961 19923 39846 100110 5112 10224 20447 40894 100111 5243 10486 20972 41943 101000 5374 10748 21496 42992 101001 5505 11010 22020 44040 101010 5636 11272 22544 45089 101011 5767 11534 23069 46137 101100 5898 11796 23593 47186
mc68331 system integration module motorola user? manual 4-15 4 4.3.3 external bus clock the state of the external clock division bit (ediv) in syncr determines clock rate for the external bus clock signal (eclk) available on pin addr23. eclk is a bus clock for mc6800 devices and peripherals. eclk frequency can be set to system clock fre- quency divided by eight or system clock frequency divided by sixteen. the clock is en- abled by the cs10 field in chip select pin assignment register 1 (cspar1). eclk operation during low-power stop is described in the following paragraph. refer to 4.8 chip selects for more information about the external bus clock. 4.3.4 low-power operation low-power operation is initiated by the cpu32. to reduce power consumption selec- tively, the cpu can set the stop bits in each module configuration register. to mini- mize overall microcontroller power consumption, the cpu can execute the lpstop instruction, which causes the sim to turn off the system clock. when individual module stop bits are set, clock signals inside each module are turned off, but module registers are still accessible. when the cpu executes lpstop, a special cpu space bus cycle writes a copy of the current interrupt mask into the clock control logic. the sim brings the mcu out of low-power operation when either an interrupt of higher priority than the stored mask or a reset occurs. refer to 4.5.4.2 lpstop broadcast cycle and section 5 cen- tral processing unit for more information. 101101 6029 12059 24117 48234 101110 6160 12321 24642 49283 101111 6291 12583 25166 50332 110000 6423 12845 25690 51380 110001 6554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 29360 58720 111000 7471 14942 2988 59769 111001 7602 15204 30409 60817 111010 7733 15466 30933 61866 111011 7864 15729 31457 62915 111100 7995 15991 31982 63963 111101 8126 16253 32506 65011 111110 8258 16515 33030 66060 111111 8389 16777 33554 67109 table 4-8 system frequencies from 32.768-khz reference (continued) to obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell. shaded cells contain values that exceed specified maximum system frequency. modulus prescaler y [w:x] = 00 [w:x] = 01 [w:x] = 10 [w:x] = 11
motorola system integration module mc68331 4-16 user? manual 4 during a low-power stop, unless the system clock signal is supplied by an external source and that source is removed, the sim clock control logic and the sim clock sig- nal (simclk) continue to operate. the periodic interrupt timer and input logic for the reset and irq pins are clocked by simclk. the sim can also continue to generate the clkout signal while in low-power mode. the stop mode system integration module clock (stsim) and stop mode external clock (stext) bits in syncr determine clock operation during low-power stop. table 4-9 is a summary of the effects of stsim and stext. modclk value is the logic level on the modclk pin during the last reset before lpstop execution. any clock in the off state is held low. if the synthesizer vco is turned off during lpstop, there is a pll relock delay after the vco is turned back on. 4.3.5 loss of reference signal the state of the reset enable (rsten) bit in syncr determines what happens when clock logic detects a reference failure. when rsten is cleared (default state out of reset), the clock synthesizer is forced into an operating condition referred to as limp mode. limp mode frequency varies from device to device, but maximum limp frequency does not exceed one half max- imum system clock when x = 0, or maximum system clock frequency when x = 1. when rsten is set, the sim resets the mcu. the limp status bit (slimp) in syncr indicates whether the synthesizer has a refer- ence signal. it is set when a reference failure is detected. table 4-9 clock control mode pins syncr bits clock status lpstop modclk extal stsim stext simclk clkout eclk no 0 external clock x x external clock external clock external clock yes 0 external clock 0 0 external clock off off yes 0 external clock 0 1 external clock external clock external clock yes 0 external clock 1 0 external clock off off yes 0 external clock 1 1 external clock external clock external clock no 1 crystal or reference x x vco vco vco yes 1 crystal or reference 0 0 crystal or reference off off yes 1 crystal or reference 0 1 crystal or reference crystal/ reference off yes 1 crystal or reference 1 0 vco off off yes 1 crystal or reference 1 1 vco vco vco
mc68331 system integration module motorola user? manual 4-17 4 4.4 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external devices. figure 4-7 shows a basic system with external memory and pe- ripherals. figure 4-7 mcu basic system the external bus has 24 address lines and 16 data lines. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the data transfer (siz1 and siz0) and data size acknowledge pins (dsack1 and dsack0 ). multiple bus cycles may be required for a transfer to or from an 8-bit port. the maximum number of bits transferred during an access is referred to as port width. widths of eight and sixteen bits can be accessed by asynchronous bus cycles con- trolled by the data size (siz[1:0]) and the data and size acknowledge (dsack[1:0] ) signals. multiple bus cycles may be required for a dynamically-sized transfer. to add flexibility and minimize the necessity for external logic, mcu chip-select logic can be synchronized with ebi transfers. refer to 4.8 chip selects for more informa- tion. 32 example sys block addr[23:0] siz clkout as fc dsack ds r/w data[15:0] cs3 cs5 irq csboot addr[15:0] siz clk dsack as ds cs data[15:0] iack irq addr[23:0] data[15:8] cs r/w memory addr[23:0] data[7:0] cs r/w memory mcu async bus peripheral 1 2 2 2 1. can be decoded to provide additional address space. 2. varies depending upon peripheral memory size.
motorola system integration module mc68331 4-18 user? manual 4 4.4.1 bus signals the address bus provides addressing information to external devices. the data bus transfers 8-bit and 16-bit data between the mcu and external devices. strobe signals, one for the address bus and another for the data bus, indicate the validity of an ad- dress and provide timing information for data. control signals indicate the beginning of each bus cycle, the address space it is to take place in, the size of the transfer, and the type of cycle. external devices decode these signals and respond to transfer data and terminate the bus cycle. the ebi operates in an asynchronous mode for any port width. 4.4.1.1 address bus bus signals addr[23:0] define the address of the byte (or the most significant byte) to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. 4.4.1.2 address strobe address strobe as is a timing signal that indicates the validity of an address on the address bus and of many control signals. it is asserted one-half clock after the begin- ning of a bus cycle. 4.4.1.3 data bus signals data[15:0 form a bidirectional, nonmultiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer eight or sixteen bits of data in one bus cycle. during a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. 4.4.1.4 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. 4.4.1.5 read/write signal the read/write signal (r/w determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. r/w only transitions when a write cycle is preceded by a read cycle or vice versa. the signal may remain low for two consecutive write cycles. 4.4.1.6 size signals size signals (siz[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe (as ) is asserted. table 4- 10 shows siz0 and siz1 encoding.
mc68331 system integration module motorola user? manual 4-19 4 4.4.1.7 function codes the cpu generates function code output signals fc[2:0] to indicate the type of activity occurring on the data or address bus. these signals can be considered address ex- tensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid while as is asserted. table 4-11 shows address space encoding. the supervisor bit in the status register determines whether the cpu is operating in supervisor or user mode. addressing mode and the instruction being executed deter- mine whether a memory access is to program or data space. 4.4.1.8 data and size acknowledge signals during normal bus transfers, external devices assert the data and size acknowledge signals (dsack[1:0] ) to indicate port width to the mcu. during a read cycle, these sig- nals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can terminate. dsack[1:0] can also be supplied internally by chip-select logic. refer to 4.8 chip selects for more information. 4.4.1.9 bus error signal the bus error signal berr is asserted when a bus cycle is not properly terminated by dsack or avec assertion. berr can also be asserted at the same time as dsack , provided the appropriate timing requirements are met. refer to 4.5.5 bus exception control cycles for more information. table 4-10 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 3 byte 0 0 long word table 4-11 address space encoding fc2 fc1 fc0 address space 0 0 0 reserved 0 0 1 user data space 0 1 0 user program space 0 1 1 reserved 1 0 0 reserved 1 0 1 supervisor data space 1 1 0 supervisor program space 1 1 1 cpu space
motorola system integration module mc68331 4-20 user? manual 4 the internal bus monitor can generate the berr signal for internal and internal-to-ex- ternal transfers. an external bus master must provide its own berr generation and drive the berr pin, because the internal berr monitor has no information about transfers initiated by an external bus master. refer to 4.5.6 external bus arbitration for more information. 4.4.1.10 halt signal the halt signal (halt ) can be asserted by an external device for debugging purposes to cause single bus cycle operation or (in combination with berr ) a retry of a bus cy- cle in error. the halt signal affects external bus cycles only, so a program not requir- ing the use of external bus may continue executing, unaffected by the halt signal. when the mcu completes a bus cycle with the halt signal asserted, data[15:0] is placed in the high-impedance state, and bus control signals are driven inactive; the ad- dress, function code, size, and read/write signals remain in the same state. if halt is still asserted once bus mastership is returned to the mcu, the address, function code, size, and read/write signals are again driven to their previous states. the mcu does not service interrupt requests while it is halted. refer to 4.5.5 bus exception control cycles for further information. 4.4.1.11 autovector signal the autovector signal avec can be used to terminate external interrupt acknowledge cycles. assertion of avec causes the cpu32 to generate vector numbers to locate an interrupt handler routine. if it is continuously asserted, autovectors are generated for all external interrupt requests. avec is ignored during all other bus cycles. refer to 4.7 interrupts for more information. avec for external interrupt requests can also be supplied internally by chip-select logic. refer to 4.8 chip selects for more information. the autovector function is disabled when there is an external bus master. refer to 4.5.6 external bus arbitration for more information. 4.4.2 dynamic bus sizing the mcu dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-bit and 16-bit ports. during an operand transfer cycle, an external device signals its port size and indicates completion of the bus cycle to the mcu through the use of the dsack inputs, as shown in table 4-12 . chip-select logic can generate data and size acknowledge sig- nals for an external device. refer to 4.8 chip selects for further information. if the cpu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to ob- table 4-12 effect of dsack signals dsack1 dsack0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?data bus port size is 8 bits 0 1 complete cycle ?data bus port size is 16 bits 0 0 reserved
mc68331 system integration module motorola user? manual 4-21 4 tain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsack signals to indicate the port width. for instance, a 16-bit device always returns dsack for a 16-bit port (regardless of wheth- er the bus cycle is a byte or word operation). dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0], and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are designated as shown in figure 4-8 . op[0:3] represent the order of access. for instance, op0 is the most significant byte of a long-word operand, and is accessed first, while op3, the least significant byte, is accessed last. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte- length operand is op0. figure 4-8 operand byte order 4.4.3 operand alignment the ebi data multiplexer establishes the necessary connections for different combi- nations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes transferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] indicate the word base address of the portion of the operand to be ac- cessed, and addr0 indicates the byte offset from the base. 4.4.4 misaligned operands cpu32 architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even address), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd ad- dress. operand byte order 31 24 23 16 15 8 7 0 long word op0 op1 op2 op3 three byte op0 op1 op2 word op0 op1 byte op0
motorola system integration module mc68331 4-22 user? manual 4 the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand through a 16-bit port, the most signif- icant operand word is transferred on the first bus cycle and the least significant oper- and word is transferred on a following bus cycle. 4.4.5 operand transfer cases table 4-13 is a summary of how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. the following paragraphs discuss all the allowable transfer cases in detail. 4.5 bus operation internal microcontroller modules are typically accessed in two system clock cycles, with no wait states. regular external bus cycles use handshaking between the mcu and external peripherals to manage transfer size and data. these accesses take three system clock cycles, again with no wait states. during regular cycles, wait states can be inserted as needed by bus control logic. refer to 4.5.2 regular bus cycles for more information. fast-termination cycles, which are two-cycle external accesses with no wait states, use chip-select logic to generate handshaking signals internally. chip-select logic can also be used to insert wait states before internal generation of handshaking signals. refer to 4.5.3 fast termination cycles and 4.8 chip selects for more information. bus control signal timing, as well as chip-select signal timing, are specified in appen- dix a electrical characteristics . refer to the sim reference manual (sim- rm/ad) for more information about each type of bus cycle. the mcu is responsible for de-skewing signals it issues at both the start and the end of a cycle. in addition, the mcu is responsible for de-skewing acknowledge and data signals from peripheral devices. 1. the cpu32 does not support misaligned transfers. 2. three-byte transfer cases occur only as a result of a long word to byte transfer. table 4-13 operand transfer cases read cycles write cycles num transfer case siz [1:0] addr0 dsack [1:0] data [15:8] data [7:0] data [15:8] data [7:0] next cycle 1 byte to 8-bit port (even/odd) 01 x 10 op0 op0 (op0) 2 byte to 16-bit port (even) 01 0 01 op0 op0 (op0) 3 byte to 16-bit port (odd) 01 1 01 op0 (op0) op0 4 word to 8-bit port (aligned) 10 0 10 op0 op0 (op1) 1 5 word to 8-bit port (misaligned) 1 10 1 10 op0 op0 (op0) 1 6 word to 16-bit port (aligned) 10 0 11 op0 op1 op0 op1 7 word to 16-bit port (misaligned) 1 10 1 01 op0 (op0) op0 2 8 long word to 8-bit port (aligned) 00 0 10 op0 op0 (op1) 13 9 long word to 8-bit port (misaligned) 1 10 1 10 op0 op0 (op0) 12 10 long word to 16-bit port (aligned) 00 0 01 op0 op1 op0 op1 6 11 long word to 16-bit port (misaligned) 1 10 1 01 op0 (op0) op0 2 12 3 byte to 8-bit port (aligned) 2 11 0 10 op0 op0 (op1) 5 13 3 byte to 8-bit port (misaligned) 2 11 1 10 op0 op0 (op0) 4
mc68331 system integration module motorola user? manual 4-23 4 4.5.1 synchronization to clkout external devices connected to the mcu bus can operate at a clock frequency different from the frequencies of the mcu as long as the external devices satisfy the interface signal timing constraints. although bus cycles are classified as asynchronous, they are interpreted relative to the mcu system clock output (clkout). descriptions are made in terms of individual system clock states, labeled {s0, s1, s2,..., sn}. the designation ?tate?refers to the logic level of the clock signal, and does not correspond to any implemented machine state. a clock cycle consists of two successive states. refer to appendix a electrical characteristics for more information. bus cycles terminated by dsack assertion normally require a minimum of three clk- out cycles. to support systems that use clkout to generate dsack and other in- puts, asynchronous input setup time and asynchronous input hold times are specified. when these specifications are met, the mcu is guaranteed to recognize the appropri- ate signal on a specific edge of the clkout signal. for a read cycle, when assertion of dsack is recognized on a particular falling edge of the clock, valid data is latched into the mcu on the next falling clock edge, provided that the data meets the data setup time. in this case, the parameter for asynchronous operation can be ignored. when a system asserts dsack for the required window around the falling edge of s2 and obeys the bus protocol by maintaining dsack and berr or halt until and throughout the clock edge that negates as , no wait states are inserted. the bus cycle runs at the maximum speed of three clocks per cycle. to ensure proper operation in a system synchronized to clkout when either berr , or berr and halt is asserted after dsack , berr (or berr and halt ) assertion must satisfy the appropriate data-in setup and hold times before the falling edge of the clock cycle after dsack is recognized. 4.5.2 regular bus cycles the following paragraphs contain a discussion of cycles that use external bus control logic. refer to 4.5.3 fast termination cycles for information about fast cycles. to initiate a transfer, the mcu asserts an address and the siz[1:0] signals. the siz signals and addr0 are externally decoded to select the active portion of the data bus (refer to 4.4.2 dynamic bus sizing ). when as , ds , and r/w are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle), then asserts a dsack[1:0] combination that indicates port size. the dsack[1:0] signals can be asserted before the data from a peripheral device is valid on a read cycle. to ensure valid data is latched into the mcu, a maximum period between dsack assertion and ds assertion is specified. there is no specified maximum for the period between the assertion of as and dsack . although the mcu can transfer data in a minimum of three clock cycles when
motorola system integration module mc68331 4-24 user? manual 4 the cycle is terminated with dsack , the mcu inserts wait cycles in clock period incre- ments until either dsack signal goes low. note the sim bus monitor asserts berr when response time exceeds a predetermined limit. bus monitor period is determined by the bmt field in sypcr. the bus monitor cannot be disabled; maximum mon- itor period is 64 system clock cycles. if no peripheral responds to an access, or if an access is invalid, external logic should assert the berr or halt signals to abort the bus cycle (when berr and halt are asserted simultaneously, the cpu32 acts as though only berr is asserted). if bus ter- mination signals are not asserted within a specified period, the bus monitor terminates the cycle. 4.5.2.1 read cycle during a read cycle, the mcu transfers data from an external memory or peripheral device. if the instruction specifies a long-word or word operation, the mcu attempts to read two bytes at once. for a byte operation, the mcu reads one byte. the portion of the data bus from which each byte is read depends on operand size, peripheral ad- dress, and peripheral port size. figure 4-9 is a flowchart of a word read cycle. refer to 4.4.2 dynamic bus sizing , 4.4.4 misaligned operands , and the sim reference manual (simrm/ad) for more information. figure 4-9 word read cycle flowchart rd cyc flow mcu peripheral address device (s0) 1) set r/w to read 2) drive address on addr[23:0] 3) drive function code on fc[2:0] 4) drive siz[1:0] for operand size start next cycle (s0) 1) decode addr, r/w , siz[1:0], ds 2) place data on data[15:0] or data[15:8] if 8-bit data present data (s2) 3) drive dsack signals terminate cycle (s5) 1) remove data from data bus 2) negate dsack assert as and ds (s1) decode dsack (s3) latch data (s4) negate as and ds (s5)
mc68331 system integration module motorola user? manual 4-25 4 4.5.2.2 write cycle during a write cycle, the mcu transfers data to an external memory or peripheral de- vice. if the instruction specifies a long-word or word operation, the mcu attempts to write two bytes at once. for a byte operation, the mcu writes one byte. the portion of the data bus upon which each byte is written depends on operand size, peripheral ad- dress, and peripheral port size. refer to 4.4.2 dynamic bus sizing and 4.4.4 misaligned operands for more infor- mation. figure 4-10 is a flowchart of a write-cycle operation for a word transfer. refer to the sim reference manual (simrm/ad) for more information. figure 4-10 write cycle flowchart 4.5.3 fast termination cycles when an external device has a fast access time, the chip-select circuit fast-termination option can provide a two-cycle external bus transfer. because the chip-select circuits wr cyc flow mcu peripheral address device (s0) 1) decode address 2) latch data from data bus accept data (s2 + s3) 3) assert dsack signals terminate cycle 1) set r/w to write 2) drive address on addr[23:0] 3) drive function code on fc[2:0] 4) drive siz[1:0] for operand size 1) negate ds and as 2) remove data from data bus terminate output transfer (s5) start next cycle assert as (s1) place data on data[15:0] (s2) assert ds and wait for dsack (s3) optional state (s4) no change 1) negate dsack
motorola system integration module mc68331 4-26 user? manual 4 are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. if multiple chip selects are to be used to select the same device that can support fast termination, and match conditions can occur simultaneously, program the dsack field in each associated chip-select option register for fast termination. alternately, pro- gram one dsack field for fast termination and the remaining dsack fields for exter- nal termination. fast termination cycles use internal handshaking signals generated by the chip-select logic. to initiate a transfer, the mcu asserts an address and the siz[1:0] signals. when as , ds , and r/w are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). at the appropriate time, chip- select logic asserts data and size acknowledge signals. the dsack option fields in the chip-select option registers determine whether inter- nally generated dsack or externally generated dsack are used. for fast termination cycles, the f-term encoding (%1110) must be used. refer to 4.8.1 chip-select reg- isters for information about fast-termination setup. to use fast-termination, an external device must be fast enough to have data ready, within the specified setup time, by the falling edge of s4. refer to appendix a elec- trical characteristics for tabular information about fast termination timing. when fast termination is in use, ds is asserted during read cycles but not during write cycles. the strb field in the chip-select option register used must be programmed with the address strobe encoding to assert the chip select signal for a fast-termination write. 4.5.4 cpu space cycles function code signals fc[2:0] designate which of eight external address spaces is ac- cessed during a bus cycle. address space 7 is designated cpu space. cpu space is used for control information not normally associated with read or write bus cycles. function codes are valid only while as is asserted. refer to 4.4.1.7 function codes for more information on codes and encoding. during a cpu space access, addr[19:16] are encoded to reflect the type of access being made. figure 4-11 shows the three encodings used by 68300 family microcon- trollers. these encodings represent breakpoint acknowledge (type $0) cycles low power stop broadcast (type $3) cycles, and interrupt acknowledge (type $f) cycles. refer to 4.7 interrupts for information about interrupt acknowledge bus cycles.
mc68331 system integration module motorola user? manual 4-27 4 figure 4-11 cpu space address encoding 4.5.4.1 breakpoint acknowledge cycle breakpoints stop program execution at a predefined point during system development. breakpoints can be used alone or in conjunction with the background debugging mode. the following paragraphs discuss breakpoint processing when background de- bugging mode is not enabled. see section 5 central processing unit for more information on exception processing and the background debugging mode. in m68300 microcontrollers, both hardware and software can initiate breakpoints. 4.5.4.1.1 software breakpoints the cpu32 bkpt instruction allows the user to insert breakpoints through software. the cpu responds to this instruction by initiating a breakpoint-acknowledge read cy- cle in cpu space. it places the breakpoint acknowledge (%0000) code on ad- dr[19:16], the breakpoint number (bits [2:0] of the bkpt opcode) in addr[4:2], and %0 (indicating a software breakpoint) on addr1. the external breakpoint circuitry decodes the function code and address lines and re- sponds by either asserting berr or placing an instruction word on the data bus and asserting dsack . if the bus cycle is terminated by dsack , the cpu32 reads the instruction on the data bus and inserts the instruction into the pipeline. (for 8-bit ports, this instruction fetch may require two read cycles.) if the bus cycle is terminated by berr , the cpu32 then performs illegal-instruction exception processing: it acquires the number of the illegal-instruction exception vector, computes the vector address from this number, loads the content of the vector address into the pc, and jumps to the exception handler routine at that address. 4.5.4.1.2 hardware breakpoints assertion of the bkpt input initiates a hardware breakpoint. the cpu responds by ini- tiating a breakpoint-acknowledge read cycle in cpu space. it places $00001e on the cpu space cyc tim 0000000000000000000 t0 bkpt# 19 23 16 000000111111111111111110 19 16 23 111 111 11111111111111111111 1 111 level 19 16 23 cpu space cycles function code 20 20 20 0 0 0 cpu space type field address bus breakpoint acknowledge low power stop broadcast interrupt acknowledge 2 41
motorola system integration module mc68331 4-28 user? manual 4 address bus. (the breakpoint acknowledge code of %0000 is placed on addr[19:16], the breakpoint number value of %111 is placed on addr[4:2], and addr1 is set to 1, indicating a hardware breakpoint.) the external breakpoint circuitry decodes the function code and address lines, places an instruction word on the data bus, and asserts berr . the cpu then performs hard- ware breakpoint exception processing: it acquires the number of the hardware break- point exception vector, computes the vector address from this number, loads the content of the vector address into the pc, and jumps to the exception handler routine at that address. if the external device asserts dsack rather than berr , the cpu ig- nores the breakpoint and continues processing. when bkpt assertion is synchronized with an instruction prefetch, processing of the breakpoint exception occurs at the end of that instruction. the prefetched instruction is ?agged?with the breakpoint when it enters the instruction pipeline, and the break- point exception occurs after the instruction executes. if the pipeline is flushed before the tagged instruction is executed, no breakpoint occurs. when bkpt assertion is syn- chronized with an operand fetch, exception processing occurs at the end of the instruc- tion during which bkpt is latched. refer to the cpu32 reference manual (cpu32rm/ad) and the sim reference man- ual (simrm/ad) for additional information.
mc68331 system integration module motorola user? manual 4-29 4 figure 4-12 breakpoint operation flowchart if breakpoint instruction executed: 1) set r/w to read 2) set function code to cpu space 3) place cpu space type 0 on addr[19:16] 4) place breakpoint number on addr[4:2] 5) clear t-bit (addr1) to zero 6) set size to word 7) assert as and ds if bkpt pin asserted: 1) set r/w to read 2) set function code to cpu space 3) place cpu space type 0 on addr[19:16] 4) place all ones on addr[4:2] 5) set t-bit (addr1) to one 6) set size to word 7) assert as and ds acknowledge breakpoint if breakpoint instruction executed and dsack is asserted: 1) latch data 2) negate as and ds 3) go to (a) if bkpt pin asserted and dsack is asserted: 1) negate as and ds 2) go to (a) if berr asserted: 1) negate as and ds 2) go to (b) (a) (b) 1) assert berr to initiate exception processing if bkpt instruction executed: 1) place latched data in instruction pipeline 2) continue processing if bkpt pin asserted: 1) continue processing if bkpt instruction executed: 1) initiate illegal instruction processing if bkpt pin asserted: 1) initiate hardware breakpoint processing 1) negate dsack or berr breakpoint operation flow cpu32 peripheral if bkpt asserted: 1) assert dsack or: 1) assert berr to initiate exception processing if bkpt instruction executed: 1) place replacement opcode on data bus 2) assert dsack or: 1110a
motorola system integration module mc68331 4-30 user? manual 4 4.5.4.2 lpstop broadcast cycle the stop bits in each module configuration register or the sim can turn off system clocks after execution of the lpstop instruction. when the cpu executes lpstop, the lpstop broadcast cycle is generated. the sim brings the mcu out of low-power mode when either an interrupt of higher priority than the stored mask or a reset occurs. refer to 4.3.4 low-power operation and section 5 central processing unit for more information. during an lpstop broadcast cycle, the cpu performs a cpu space write to address $3fffe. this write puts a copy of the interrupt mask value in the clock control logic. the mask is encoded on the data bus as shown in figure 4-13 . the lpstop cpu space cycle is shown externally (if the bus is available) as an indication to external de- vices that the mcu is going into low-power stop mode. the sim provides an internally generated dsack response to this cycle. the timing of this bus cycle is the same as for a fast write cycle. figure 4-13 lpstop interrupt mask level 4.5.5 bus exception control cycles an external device or a chip-select circuit must assert at least one of the dsack[1:0] signals or the avec signal to terminate a bus cycle normally. bus error processing oc- curs when bus cycles are not terminated in the expected manner. the internal bus monitor can be used to generate berr internally, causing a bus error exception to be taken. bus cycles can also be terminated by assertion of the external berr or halt signal, or by assertion of the two signals simultaneously. acceptable bus cycle termination sequences are summarized as follows. the case numbers refer to table 4-14 , which indicates the results of each type of bus cycle ter- mination. normal termination dsack is asserted; berr and halt remain negated (case 1). halt termination halt is asserted at the same time or before dsack , and berr remains negated (case 2). bus error termination berr is asserted in lieu of, at the same time as, or before dsack (case 3), or after dsack (case 4), and halt remains negated; berr is negated at the same time or after dsack . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ip mask
mc68331 system integration module motorola user? manual 4-31 4 retry termination halt and berr are asserted in lieu of, at the same time as, or before dsack (case 5) or after dsack (case 6); berr is negated at the same time or after dsack ; halt may be negated at the same time or after berr . table 4-14 shows various combinations of control signal sequences and the resulting bus cycle terminations. notes: n = the number of current even bus state (s2, s4, etc.). a = signal is asserted in this bus state. na = signal is not asserted in this state. x = don't care. s = signal was asserted in previous state and remains asserted in this state. to properly control termination of a bus cycle for a retry or a bus error condition, dsack , berr , and halt must be asserted and negated with the rising edge of the mcu clock. this ensures that when two signals are asserted simultaneously, the re- quired setup time and hold time for both of them are met for the same falling edge of the mcu clock. (refer to appendix a electrical characteristics for timing requirements.) external circuitry that provides these signals must be designed with these constraints in mind, or else the internal bus monitor must be used. dsack , berr , and halt may be negated after as is negated. warning if dsack or berr remain asserted into s2 of the next bus cycle, that cycle may be terminated prematurely. table 4-14 dsack , berr , and halt assertion results case number control signal asserted on rising edge of state result n n + 2 1 dsack berr halt a na na s na x normal termination. 2 dsack- berr halt a na a/s s na s halt termination: normal cycle terminate and halt. continue when halt is negated. 3 dsack- berr halt na/a a na x s x bus error termination: terminate and take bus error exception, possibly deferred. 4 dsack- berr halt a a na x s na bus error termination: terminate and take bus error exception, possibly deferred. 5 dsack- berr halt na/a a a/s x s s retry termination: terminate and retry when halt is negated. 6 dsack- berr halt a na na x a a retry termination: terminate and retry when halt is negated.
motorola system integration module mc68331 4-32 user? manual 4 4.5.5.1 bus errors the cpu32 treats bus errors as a type of exception. bus error exception processing begins when the cpu detects assertion of the imb berr signal (by the internal bus monitor or an external source) while the halt signal remains negated. berr assertions do not force immediate exception processing. the signal is synchro- nized with normal bus cycles and is latched into the cpu32 at the end of the bus cycle in which it was asserted. because bus cycles can overlap instruction boundaries, bus error exception processing may not occur at the end of the instruction in which the bus cycle begins. timing of berr detection/acknowledge is dependent upon several fac- tors: ?which bus cycle of an instruction is terminated by assertion of berr . ?the number of bus cycles in the instruction during which berr is asserted. ?the number of bus cycles in the instruction following the instruction in which berr is asserted. ?whether berr is asserted during a program space access or a data space ac- cess. because of these factors, it is impossible to predict precisely how long after occur- rence of a bus error the bus error exception is processed. caution the external bus interface does not latch data when an external bus cycle is terminated by a bus error. when this occurs during an in- struction prefetch, the imb precharge state (bus pulled high, or $ff) is latched into the cpu32 instruction register, with indeterminate re- sults. 4.5.5.2 double bus faults exception processing for bus error exceptions follows the standard exception process- ing sequence. refer to section 5 central processing unit for more informa- tion about exceptions. however, a special case of bus error, called double bus fault, can abort exception processing. berr assertion is not detected until an instruction is complete. the berr latch is cleared by the first instruction of the berr exception handler. double bus fault occurs in two ways: 1. when bus error exception processing begins and a second berr is detected before the first instruction of the first exception handler is executed. 2. when one or more bus errors occur before the first instruction after a reset exception is executed. 3. a bus error occurs while the cpu32 is loading information from a bus error stack frame during a return from exception (rte) instruction. multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed.
mc68331 system integration module motorola user? manual 4-33 4 immediately after assertion of a second berr , the mcu halts and drives the halt line low. only a reset can restart a halted mcu. however, bus arbitration can still occur (refer to 4.5.6 external bus arbitration ). a bus error or address error that occurs after exception processing has been completed (during the execution of the exception han- dler routine, or later) does not cause a double bus fault. the mcu continues to retry the same bus cycle as long as the external hardware requests it. 4.5.5.3 retry operation berr and halt during a bus cycle, the mcu enters the retry sequence. a delayed retry can also occur. the mcu terminates the bus cycle, places the as and ds signals in their inactive state, and does not begin another bus cycle until the berr and halt signals are negated by external logic. after a synchronization delay, the mcu retries the previous cycle using the same address, function codes, data (for a write), and con- trol signals. the berr signal should be negated before s2 of the read cycle to ensure correct operation of the retried cycle. if br , berr , and halt are all asserted on the same cycle, the ebi will enter the rerun sequence but first relinquishes the bus to an external master. once the external mas- ter returns the bus and negates berr and halt , the ebi runs the previous bus cycle. this feature allows an external device to correct the problem that caused the bus error and then try the bus cycle again. the mcu retries any read or write cycle of an indivisible read-modify-write operation separately; rmc remains asserted during the entire retry sequence. the mcu will not relinquish the bus while rmc is asserted. any device that requires the mcu to give up the bus and retry a bus cycle during a read-modify-write cycle must assert berr and br only (halt must remain negated). the bus error handler software should examine the read-modify-write bit in the special status word and take the appropriate action to resolve this type of fault when it occurs. 4.5.5.4 halt operation when halt is asserted while berr is not asserted, the mcu halts external bus ac- tivity after negation of dsack . the mcu may complete the current word transfer in progress. for a long-word to byte transfer, this could be after s2 or s4. for a word to byte transfer, activity ceases after s2. negating and reasserting halt according to timing requirements provides single-step (bus cycle to bus cycle) operation. the halt signal affects external bus cycles only, so that a program that does not use external bus can continue executing. during dy- namically-sized 8-bit transfers, external bus activity may not stop at the next cycle boundary. occurrence of a bus error while halt is asserted causes the cpu32 to ini- tiate a retry sequence. when the mcu completes a bus cycle while the halt signal is asserted, the data bus goes to high-impedance state and the as and ds signals are driven to their inactive states. address, function code, size, and read/write signals remain in the same state.
motorola system integration module mc68331 4-34 user? manual 4 the halt operation has no effect on bus arbitration (refer to 4.5.6 external bus arbi- tration ). however, when external bus arbitration occurs while the mcu is halted, ad- dress and control signals go to high-impedance state. if halt is still asserted when the mcu regains control of the bus, address, function code, size, and read/write sig- nals revert to the previous driven states. the mcu cannot service interrupt requests while halted. 4.5.6 external bus arbitration mcu bus design provides for a single bus master at any one time. either the mcu or an external device can be master. bus arbitration protocols determine when an exter- nal device can become bus master. bus arbitration requests are recognized during normal processing, halt assertion, and when the cpu has halted due to a double bus fault. the bus controller in the mcu manages bus arbitration signals so that the mcu has the lowest priority. external devices that need to obtain the bus must assert bus arbi- tration signals in the sequences described in the following paragraphs. systems that include several devices that can become bus master require external cir- cuitry to assign priorities to the devices, so that when two or more external devices at- tempt to become bus master at the same time, the one having the highest priority becomes bus master first. the protocol sequence is: 1. an external device asserts bus request signal (br ); 2. the mcu asserts the bus grant signal (bg ) to indicate that the bus is available; 3. an external device asserts the bus grant acknowledge (bgack ) signal to indi- cate that it has assumed bus mastership. br can be asserted during a bus cycle or between cycles. bg is asserted in response to br . to guarantee operand coherency, bg is only asserted at the end of operand transfer. additionally, bg is not asserted until the end of an indivisible read-modify- write operation (when rmc is negated). if more than one external device can be bus master, required external arbitration must begin when a requesting device receives bg . an external device must assert bgack when it assumes mastership, and must maintain bgack assertion as long as it is bus master. two conditions must be met for an external device to assume bus mastership. the de- vice must receive bg through the arbitration process, and bgack must be inactive, indicating that no other bus master is active. this technique allows the processing of bus requests during data transfer cycles. bg is negated a few clock cycles after bgack transition. however, if bus requests are still pending after bg is negated, the mcu asserts bg again within a few clock cycles. this additional bg assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus. refer to figure 4-14 , which shows bus arbitration for a single device. the flowchart shows br negated at the same time bgack is asserted.
mc68331 system integration module motorola user? manual 4-35 4 figure 4-14 bus arbitration flowchart for single request state changes occur on the next rising edge of clkout after the internal signal is val- id. the bg signal transitions on the falling edge of the clock after a state is reached during which g changes. the bus control signals (controlled by t) are driven by the mcu immediately following a state change, when bus mastership is returned to the mcu. state 0, in which g and t are both negated, is the state of the bus arbiter while the mcu is bus master. request r and acknowledge a keep the arbiter in state 0 as long as they are both negated. 4.5.6.1 slave (factory test) mode arbitration this mode is used for factory production testing of internal modules. it is not supported as a user operating mode. slave mode is enabled by holding data11 low during re- set. in slave mode, when bg is asserted, the mcu is slaved to an external master that has full access to all internal registers. 4.5.6.2 show cycles the mcu normally performs internal data transfers without affecting the external bus, but it is possible to show these transfers during debugging. as is not asserted exter- nally during show cycles. grant bus arbitration 1) assert bus grant (bg ) terminate arbitration 1) negate bg (and wait for bgack to be negated) re-arbitrate or resume processor operation mcu requesting device request the bus 1) assert bus request (br ) acknowledge bus mastership 1) external arbitration determines next bus master 2) next bus master waits for bgack to be negated 3) next bus master asserts bgack to become new master 4) bus master negates br operate as bus master 1) perform data transfers (read and write cycles) according to the same rules the processor uses release bus mastership 1) negate bgack bus arb flow
motorola system integration module mc68331 4-36 user? manual 4 show cycles are controlled by the shen field in the simcr (refer to 4.2.3 show in- ternal cycles ). this field is cleared by reset. when show cycles are disabled, the ad- dress bus, function codes, size, and read/write signals reflect internal bus activity, but as and ds are not asserted externally and external data bus pins are in high-imped- ance state during internal accesses. when show cycles are enabled, ds is asserted externally during internal cycles, and internal data is driven out on the external data bus. because internal cycles normally continue to run when the external bus is granted, one shen encoding halts internal bus activity while there is an external master. siz[1:0] signals reflect bus allocation during show cycles. only the appropriate portion of the data bus is valid during the cycle. during a byte write to an internal address, the portion of the bus that represents the byte that is not written reflects internal bus con- ditions, and is indeterminate. during a byte write to an external address, the data mul- tiplexer in the sim causes the value of the byte that is written to be driven out on both bytes of the data bus. 4.6 reset reset occurs when an active low logic level on the reset pin is clocked into the sim. the reset input is synchronized to the system clock. if there is no clock when re- set is asserted, reset does not occur until the clock starts. resets are clocked to allow completion of write cycles in progress at the time reset is asserted. reset procedures handle system initialization and recovery from catastrophic failure. the mcu performs resets with a combination of hardware and software. the system integration module determines whether a reset is valid, asserts control signals, per- forms basic system configuration and boot rom selection based on hardware mode- select inputs, then passes control to the cpu32. 4.6.1 reset exception processing the cpu32 processes resets as a type of asynchronous exception. an exception is an event that preempts normal processing, and can be caused by internal or external events. exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. each exception has an assigned vector that points to an associated handler routine. these vectors are stored in the vector base register (vbr). the vbr contains the base address of a 1024-byte excep- tion vector table, which consists of 256 exception vectors. the cpu32 uses vector numbers to calculate displacement into the table. refer to section 5 central processing unit for more information concerning exceptions. reset is the highest-priority cpu32 exception. unlike all other exceptions, a reset oc- curs at the end of a bus cycle, and not at an instruction boundary. handling resets in this way prevents write cycles in progress at the time the reset signal is asserted from being corrupted. however, any processing in progress is aborted by the reset excep- tion, and cannot be restarted. only essential reset tasks are performed during excep- tion processing. other initialization tasks must be accomplished by the exception handler routine. 4.6.8 reset processing summary contains details of exception pro- cessing.
mc68331 system integration module motorola user? manual 4-37 4 4.6.2 reset control logic sim reset control logic determines the cause of a reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate re- set lines. reset control logic can drive four different internal signals. 1. extrst (external reset) drives the external reset pin. 2. clkrst (clock reset) resets the clock module. 3. mstrst (master reset) goes to all other internal circuits. 4. sysrst (system reset) indicates to internal circuits that the cpu has executed a reset instruction. all resets are gated by clkout. resets are classified as synchronous or asynchro- nous. an asynchronous reset can occur on any clkout edge. reset sources that cause an asynchronous reset usually indicate a catastrophic failure; thus the reset control logic responds by asserting reset to the system immediately. (a system reset, however, caused by the cpu32 reset instruction, is asynchronous but does not in- dicate any type of catastrophic failure). synchronous resets are timed (clkout) to occur at the end of bus cycles. the inter- nal bus monitor is automatically enabled for synchronous resets. when a bus cycle does not terminate normally, the bus monitor terminates it. refer to table 4-15 for a summary of reset sources. internal single byte or aligned word writes are guaranteed valid for synchronous re- sets. external writes are also guaranteed to complete, provided the external configu- ration logic on the data bus is conditioned as shown in figure 4-15 . 4.6.3 reset mode selection the logic states of certain data bus pins during reset determine sim operating config- uration. in addition, the state of the modclk pin determines system clock source and the state of the bkpt pin determines what happens during subsequent breakpoint as- sertions. table 4-16 is a summary of reset mode selection options. table 4-15 reset source summary type source timing cause reset lines asserted by controller external external synch external signal mstrst clkrst extrst power up ebi asynch v dd mstrst clkrst extrst software watchdog monitor asynch time out mstrst clkrst extrst halt monitor asynch internal halt assertion (e.g. double bus fault) mstrst clkrst extrst loss of clock clock synch loss of reference mstrst clkrst extrst test test synch test mode mstrst extrst system cpu32 asynch reset instruction extrst
motorola system integration module mc68331 4-38 user? manual 4 4.6.3.1 data bus mode selection all data lines have weak internal pull-up drivers. when pins are held high by the inter- nal drivers, the mcu uses a default operating configuration. however, specific lines can be held low externally to achieve an alternate configuration. note external bus loading can overcome the weak internal pull-up drivers on data bus lines, and hold pins low during reset. use an active device to hold data bus lines low. data bus configuration logic must re- lease the bus before the first bus cycle after reset to prevent conflict with external memory devices. the first bus cycle occurs ten clkout cycles after reset is re- leased. if external mode selection logic causes a conflict of this type, an isolation re- sistor on the driven lines may be required. figure 4-15 shows a recommended method for conditioning the mode select signals. table 4-16 reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboot 16-bit csboot 8-bit data1 cs0 cs1 cs2 br bg bgack data2 cs3 cs4 cs5 fc0 fc1 fc2 data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] data8 dsack[1:0] , avec , ds , as , size porte data9 irq[7:1] modclk portf data11 test mode disabled test mode enabled modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled
mc68331 system integration module motorola user? manual 4-39 4 figure 4-15 data bus mode select conditioning data bus mode select current is specified in appendix a electrical charac- teristics . do not confuse pin function with pin electrical state. refer to 4.6.5 pin state during reset for more information. data0 determines the function of the boot rom chip-select signal (csboot ). unlike other chip-select signals, csboot is active at the release of reset. during reset ex- ception processing, the mcu fetches initialization vectors beginning at address $000000 in supervisor program space. an external memory device containing vectors located at these addresses can be enabled by csboot after a reset. the logic level of data0 during reset selects boot rom port size for dynamic bus allocation. when data0 is held low, port size is eight bits; when data0 is held high, either by the weak internal pull-up driver or by an external pull-up, port size is 16 bits. refer to 4.8.4 chip- select reset operation for more information. data1 and data2 determine the functions of cs[2:0] and cs[5:3] , respectively. da- ta[7:3] determine the functions of an associated chip select and all lower-numbered chip-selects down through cs6 . for example, if data5 is pulled low during reset, cs[8:6] are assigned alternate function as addr[21:19], and cs[10:9] remain chip- selects. refer to 4.8.4 chip-select reset operation for more information. data8 determines the function of the dsack[1:0] , avec , ds , as , and size pins. if data8 is held low during reset, these pins are assigned to i/o port e. data9 determines the function of interrupt request pins irq[7:0] and the clock mode select pin (modclk). when data9 is held low during reset, these pins are assigned to i/o port f. data11 determines whether the sim operates in test mode out of reset. this capabil- ity is used for factory testing of the mcu. data bus mode decode reset r/w mode select lines ds v dd v dd data15 data1 data0 * * * * optional, to prevent conflict on reset negation.
motorola system integration module mc68331 4-40 user? manual 4 4.6.3.2 clock mode selection the state of the clock mode (modclk) pin during reset determines what clock source the mcu uses. when modclk is held high during reset, the clock signal is generated from a reference frequency. when modclk is held low during reset, the clock syn- thesizer is disabled, and an external system clock signal must be applied. refer to 4.3 system clock for more information. note the modclk pin can also be used as parallel i/o pin pf0. to pre- vent inadvertent clock mode selection by logic connected to port f, use an active device to drive modclk during reset. 4.6.3.3 breakpoint mode selection the mcu uses internal and external breakpoint (bkpt ) signals. during reset excep- tion processing, at the release of the reset signal, the cpu32 samples these signals to determine how to handle breakpoints. if either bkpt signal is at logic level zero when sampled, an internal bdm flag is set, and the cpu32 enters background debugging mode whenever either bkpt input is subsequently asserted. if both bkpt inputs are at logic level one when sampled, breakpoint exception pro- cessing begins whenever either bkpt signal is subsequently asserted. refer to section 5 central processing unit for more information on back- ground debugging mode and exceptions. refer to 4.5.4 cpu space cycles for infor- mation concerning breakpoint acknowledge bus cycles. 4.6.4 mcu module pin function during reset usually, module pins default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control regis- ters, and by clearing the appropriate port data direction registers. refer to individual module sections in this manual for more information. table 4-17 is a summary of mod- ule pin function out of reset. refer to appendix d register summary for register function and reset state.
mc68331 system integration module motorola user? manual 4-41 4 4.6.5 pin state during reset it is important to keep the distinction between pin function and pin electrical state clear. although control register values and mode select inputs determine pin function, a pin driver can be active, inactive or in high-impedance state while reset occurs. during power-up reset, pin state is subject to the constraints discussed in 4.6.7 power-on reset . note pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. this de- creases additional i dd caused by digital inputs floating near mid-sup- ply level. 4.6.5.1 reset states of sim pins generally, while reset is asserted, sim pins either go to an inactive high-impedance state or are driven to their inactive states. after reset is released, mode selection occurs, and reset exception processing begins. pins configured as inputs during reset become active high-impedance loads after reset is released. inputs must be driven to the desired active state. pull-up or pull-down circuitry may be necessary. pins con- figured as outputs begin to function after reset is released. table 4-18 is a summary of sim pin states during reset. table 4-17 module pin functions module pin mnemonic function cpu32 dsi/ifetch dsi/ifetch dso/ipipe dso/ipipe bkpt /dsclk bkpt /dsclk gpt pgp7/ic4/oc5 discrete input pgp[6:3]/oc[4:1] discrete input pgp[2:0]/ic[3:1] discrete input pai discrete input pclk discrete input pwma, pwmb discrete output qsm pqs7/txd discrete input pqs[6:4]/pcs[3:1] discrete input pqs3/pcs0/ss discrete input pqs2/sck discrete input pqs1/mosi discrete input pqs0/miso discrete input rxd rxd
motorola system integration module mc68331 4-42 user? manual 4 4.6.5.2 reset states of pins assigned to other mcu modules as a rule, module pins that are assigned to general-purpose i/o ports go to active high- impedance state following reset. other pin states are determined by individual module control register settings. refer to sections concerning modules for details. however, during power-up reset, module port pins may be in an indeterminate state for a short period. refer to 4.6.7 power-on reset for more information. 4.6.6 reset timing the reset input must be asserted for a specified minimum period for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. while reset is asserted, sim pins are either in an inactive, high impedance state or are driven to their inactive states. when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. table 4-18 sim pin reset states state while pin state after reset released mnemonic reset asserted pin function pin state pin function pin state cs10 /addr23 1 cs10 1 addr23 unknown cs[9:6] /addr[22:19]/pc[6:3] 1 cs[9:6] 1 addr[22:19] unknown addr[18:0] high-z output addr[18:0] unknown addr[18:0] unknown as /pe5 high-z output as output pe5 input avec /pe2 disabled avec input pe2 input berr disabled berr input berr input csm /bg 1 csm 1bg 1 cse /bgack 1 cse 1 bgack input cs0 /br 1 cs0 1br input clkout output clkout output clkout output csboot 1 csboot 0 csboot 0 data[15:0] mode select data[15:0] input data[15:0] input ds /pe4 disabled ds output pe4 input dsack0 /pe0 disabled dsack0 input pe0 input dsack1 /pe1 disabled dsack1 input pe1 input cs5 /fc2/pc2 1 cs5 1 fc2 unknown fc1/pc1 1 fc1 1 fc1 unknown cs3 /fc0/pc0 1 cs3 1 fc0 unknown halt disabled halt input halt input irq[7:1] /pf[7:1] disabled irq[7:1] input pf[7:1] input modclk/pf0 mode select modclk input pf0 input r/w disabled r/w output r/w output reset asserted reset input reset input rmc disabled rmc output pe3 input siz[1:0]/pe[7:6] disabled siz[1:0] unknown pe[7:6] input tsc mode select tsc input tsc input
mc68331 system integration module motorola user? manual 4-43 4 if an internal source asserts a reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cycles. at the end of this 10-cycle period, the reset input is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cy- cles. at the end of this period, the pin again goes to high-impedance state for ten cy- cles, then it is tested again. the process repeats until reset is released. 4.6.7 power-on reset when the sim clock synthesizer is used to generate system clocks, power-on reset in- volves special circumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer pow- er input pin v ddsyn for the mcu to operate. the following discussion assumes that v ddsyn is applied before and during reset, which minimizes crystal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal pa- rameters and by oscillator circuit design. v dd ramp-up time also affects pin state dur- ing reset. refer to appendix a electrical characteristics for voltage and timing specifications. during power-on reset, an internal circuit in the sim drives the imb internal (mstrst) and external (extrst) reset lines. the circuit releases mstrst as v dd ramps up to the minimum specified value, and sim pins are initialized as shown in table 4-19 . as v dd reaches specified minimum value, the clock synthesizer vco begins operation and clock frequency ramps up to specified limp mode frequency. the external reset line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. the sim clock synthesizer provides clock signals to the other mcu modules. after the clock is running and mstrst is asserted for at least four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long the four cy- cles take. worst case is approximately 15 milliseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by external pull-up resistors, external logic on input/output or output-only pins during this time must condition the lines. active drivers require high-impedance buffers or isolation resistors to prevent conflict. figure 4-16 is a timing diagram of power-up reset. it shows the relationships between reset , v dd , and bus signals.
motorola system integration module mc68331 4-44 user? manual 4 figure 4-16 power-on reset 4.6.8 reset processing summary to prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary. any processing in progress at the time a reset occurs is aborted. after sim reset control logic has synchronized an internal or external reset request, it asserts the mstrst signal. the following events take place when mstrst is asserted. a. instruction execution is aborted. b. the status register is initialized. 1. the t0 and t1 bits are cleared to disable tracing. 2. the s bit is set to establish supervisor privilege level. 3. the interrupt priority mask is set to $7, disabling all interrupts below priority 7. c. the vector base register is initialized to $000000. the following events take place when mstrst is negated after assertion. a. the cpu32 samples the bkpt input. b. the cpu32 fetches the reset vector: 1. the first long word of the vector is loaded into the interrupt stack pointer. 2. the second long word of the vector is loaded into the program counter. vectors can be fetched from internal ram or from external rom enabled by the csboot signal. c. the cpu32 fetches and begins decoding the first instruction to be executed. 32 por tim clkout vco lock bus cycles reset v dd 1 bus state unknown address and control signals three-stated 512 clocks notes: 1. internal start-up time. 2. ssp fetched. 3. pc fetched. 4. first instruction fetched. 10 clocks 4 3 2
mc68331 system integration module motorola user? manual 4-45 4 4.6.9 reset status register the reset status register (rsr) contains a bit for each reset source in the mcu. when a reset occurs, a bit corresponding to the reset type is set. when multiple causes of reset occur at the same time, more than one bit in rsr may be set. the reset status register is updated by the reset control logic when the reset signal is released. refer to appendix d register summary . 4.7 interrupts interrupt recognition and servicing involve complex interaction between the system in- tegration module, the central processing unit, and a device or module requesting in- terrupt service. this discussion provides an overview of the entire interrupt process. chip-select logic can also be used to respond to interrupt requests. refer to 4.8 chip selects for more information. 4.7.1 interrupt exception processing the cpu32 processes resets as a type of asynchronous exception. an exception is an event that preempts normal processing. each exception has an assigned vector in an exception vector table that points to an associated handler routine. the cpu uses vector numbers to calculate displacement into the table. during exception processing, the cpu fetches the appropriate vector and executes the exception handler routine to which the vector points. out of reset, the exception vector table is located beginning at address $000000. this value can be changed by programming the vector base register (vbr) with a new val- ue, and multiple vector tables can be used. refer to section 5 central pro- cessing unit for more information concerning exceptions. 4.7.2 interrupt priority and recognition the cpu32 provides eight levels of interrupt priority. all interrupts with priorities less than seven can be masked by the interrupt priority (ip) field in status register. there are seven interrupt request signals (irq[7:1] ). these signals are used internally on the imb, and are corresponding pins for external interrupt service requests. the cpu treats all interrupt requests as though they come from internal modules ?exter- nal interrupt requests are treated as interrupt service requests from the sim. each of the interrupt request signals corresponds to an interrupt priority level. irq1 has the lowest priority and irq7 the highest. interrupt recognition is determined by interrupt priority level and interrupt priority mask value, interrupt recognition is determined by interrupt priority level and interrupt priority mask value. the interrupt priority mask consists of three bits in the cpu32 status reg- ister. binary values %000 to %111 provide eight priority masks. masks prevent an in- terrupt request of a priority less than or equal to the mask value from being recognized and processed. irq7 , however, is always recognized, even if the mask value is %111. irq[7:1] are active-low level-sensitive inputs. the low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected.
motorola system integration module mc68331 4-46 user? manual 4 irq7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the irq7 line. this prevents redundant servicing and stack overflow. a nonmaskable interrupt is generated each time irq7 is asserted as well as each time the priority mask changes from %111 to a lower number while irq7 is asserted. interrupt requests are sampled on consecutive falling edges of the system clock. in- terrupt request input circuitry has hysteresis: to be valid, a request signal must be as- serted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pending requests are pro- cessed at instruction boundaries or when exception processing of higher-priority ex- ceptions is complete. the cpu32 does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pend- ing, the higher priority request is serviced. if an interrupt request with a priority equal to or lower than the current ip mask value is made, the cpu32 does not recognize the occurrence of the request. if simultaneous interrupt requests of different priorities are made, and both have a priority greater than the mask value, the cpu32 recognizes the higher-level request. 4.7.3 interrupt acknowledge and arbitration when the cpu32 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a cpu space read cycle. the request level serves two purposes: it is de- coded by modules or external devices that have requested interrupt service, to deter- mine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the interrupt priority mask field in the cpu32 status register, to preclude further interrupts of lower priority during interrupt service. modules or external devices that have requested interrupt service must decode the in- terrupt priority mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value. however, before modules or external devices respond, interrupt arbitration takes place. arbitration is performed by means of serial contention between values stored in indi- vidual module interrupt arbitration (iarb) fields. each module that can make an inter- rupt service request, including the sim, has an iarb field in its configuration register. iarb fields can be assigned values from %0000 to %1111. in order to implement an arbitration scheme, each module that can initiate an interrupt service request must be assigned a unique, non-zero iarb field value during system initialization. arbitration priorities range from %0001 (lowest) to %1111 (highest) ?if the cpu recognizes an interrupt service request from a source that has an iarb field value of %0000, a spu- rious interrupt exception is processed. warning do not assign the same arbitration priority to more than one module. when two or more iarb fields have the same nonzero value, the
mc68331 system integration module motorola user? manual 4-47 4 cpu32 interprets multiple vector numbers at the same time, with un- predictable consequences. because the ebi manages external interrupt requests, the sim iarb value is used for arbitration between internal and external interrupt requests. the reset value of iarb for the sim is %1111, and the reset iarb value for all other modules is %0000. although arbitration is intended to deal with simultaneous requests of the same prior- ity, it always takes place, even when a single source is requesting service. this is im- portant for two reasons: the ebi does not transfer the interrupt acknowledge read cycle to the external bus unless the sim wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error. when arbitration is complete, the module with the highest arbitration priority must ter- minate the bus cycle. internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals. in the case of an ex- ternal interrupt request, after the interrupt acknowledge cycle is transferred to the ex- ternal bus, the appropriate external device must decode the mask value and respond with a vector number, then generate data and size acknowledge (dsack ) termination signals, or it must assert the autovector (avec ) request signal. if the device does not respond in time, the ebi bus monitor asserts the bus error signal berr , and a spuri- ous interrupt exception is taken. chip-select logic can also be used to generate internal avec or dsack signals in re- sponse to interrupt requests from external devices (refer to 4.8.3 using chip-select signals for interrupt acknowledge ). chip-select address match logic functions only after the ebi transfers an interrupt acknowledge cycle to the external bus following iarb contention. if a module makes an interrupt request of a certain priority, and the appropriate chip-select registers are programmed to generate avec or dsack sig- nals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates internal cycle termination signals. for periodic timer interrupts, the pirq field in the periodic interrupt control register (pi- cr) determines pit priority level. a pirq value of %000 means that pit interrupts are inactive. by hardware convention, when the cpu32 receives simultaneous interrupt requests of the same level from more than one sim source (including external devic- es), the periodic interrupt timer is given the highest priority, followed by the irq pins. 4.7.4 interrupt processing summary a summary of the entire interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending. a. the cpu finishes higher priority exception processing or reaches an instruction boundary. b. the processor state is stacked. the s bit in the status register is set, establish- ing supervisor access level, and bits t1 and t0 are cleared, disabling tracing. c. the interrupt acknowledge cycle begins: 1. fc[2:0] are driven to %111 (cpu space) encoding.
motorola system integration module mc68331 4-48 user? manual 4 2. the address bus is driven as follows: addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %111111111111; addr[3:1] = the priority of the interrupt request being acknowledged; and addr0 = %1. 3. the request level is latched from the address bus into the interrupt priority mask field in the status or condition code register. d. modules that have requested interrupt service decode the priority value in ad- dr[3:1]. if request priority is the same as acknowledged priority, arbitration by iarb contention takes place. e. after arbitration, the interrupt acknowledge cycle is completed in one of the fol- lowing ways: 1. when there is no contention (iarb = %0000), the spurious interrupt moni- tor asserts berr , and the cpu generates the spurious interrupt vector number. 2. the dominant interrupt source supplies a vector number and dsack sig- nals appropriate to the access. the cpu acquires the vector number. 3. the avec signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the cpu generates an au- tovector number corresponding to interrupt priority. 4. the bus monitor asserts berr and the cpu32 generates the spurious in- terrupt vector number. f. the vector number is converted to a vector address. g. the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 4.7.5 interrupt acknowledge bus cycles interrupt acknowledge bus cycles are cpu32 space cycles that are generated during exception processing. for further information about the types of interrupt acknowledge bus cycles determined by avec or dsack , refer to appendix a electrical characteristics and the sim reference manual (simrm/ad). 4.8 chip selects typical microcontrollers require additional hardware to provide external select and ad- dress decode signals. the mcu includes 12 programmable chip-select circuits that can provide 2- to 20-clock-cycle access to external memory and peripherals. address block sizes of two kbytes to one mbyte can be selected. figure 4-17 is a diagram of a basic system that uses chip selects.
mc68331 system integration module motorola user? manual 4-49 4 figure 4-17 basic mcu system chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. chip select logic can also generate dsack and avec signals internally. each signal can also be synchronized with the eclk signal available on addr23. when a memory access occurs, chip-select logic compares address space type, ad- dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac- knowledge) to parameters stored in chip-select registers. if all parameters match, the appropriate chip-select signal is asserted. select signals are active low. if a chip-select function is given the same address as a microcontroller module or an internal memory array, an access to that address goes to the module or array, and the chip-select sig- nal is not asserted. the external address and data buses do not reflect the internal ac- cess. all chip-select circuits are configured for operation out of reset. however, all chip-se- lect signals except csboot are disabled, and cannot be asserted until the byte field in the corresponding option register is programmed to a nonzero value, selecting a 32 example sys block addr[23:0] siz clkout as fc dsack ds r/w data[15:0] cs3 cs5 irq csboot addr[15:0] siz clk dsack as ds cs data[15:0] iack irq addr[23:0] data[15:8] cs r/w memory addr[23:0] data[7:0] cs r/w memory mcu async bus peripheral 1 2 2 2 1. can be decoded to provide additional address space. 2. varies depending upon peripheral memory size.
motorola system integration module mc68331 4-50 user? manual 4 transfer size. the chip-select option must not be written until a base address has been written to a proper base address register. csboot is automatically asserted out of reset. alternate functions for chip-select pins are enabled if appropriate data bus pins are held low at the release of the reset signal (refer to 4.6.3.1 data bus mode selec- tion for more information). figure 4-18 is a functional diagram of a single chip-select circuit. figure 4-18 chip-select circuit block diagram 4.8.1 chip-select registers each chip-select pin can have one or more functions. ship-select pin assignment reg- isters (cspar[0:1]) determine functions of the pins. pin assignment registers also de- termine port size (8- or 16-bit) for dynamic bus allocation. a pin data register (portc) latches data for chip-select pins that are used for discrete output. blocks of addresses are assigned to each chip-select function. block sizes of two kbytes to one mbyte can be selected by writing values to the appropriate base address register (csbar[0:10], csbarbt). address blocks for separate chip-select functions can overlap. chip select option registers (csor[0:10], csorbt) determine timing of and condi- tions for assertion of chip-select signals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization software usually resides in a peripheral memory device controlled by the chip-select circuits. a set of special chip-select functions and registers (csorbt, cs- barbt) is provided to support bootstrap operation. comprehensive address maps and register diagrams are provided in appendix d register summary . chip sel block avec generator dsack generator pin assignment register pin data register base address register timing and control address comparator option compare option register avec dsack pin bus control internal signals address
mc68331 system integration module motorola user? manual 4-51 4 4.8.1.1 chip-select pin assignment registers the pin assignment registers contain twelve 2-bit fields (cs[10:0] and csboot ) that determine the functions of the chip-select pins. each pin has two or three possible functions, as shown in table 4-19 . table 4-20 shows pin assignment field encoding. pins that have no discrete output function do not use the %00 encoding. port size determines the way in which bus transfers to an external address are allo- cated. port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip select. port size and transfer size affect how the chip-select signal is asserted. refer to 4.8.1.3 chip-select option registers for more information. out of reset, chip-select pin function is determined by the logic level on a correspond- ing data bus pin. these pins have weak internal pull-up drivers, but can be held low by external devices. (refer to 4.6.3.1 data bus mode selection for more informa- tion.) either 16-bit chip-select function (%11) or alternate function (%01) can be select- ed during reset. all pins except the boot rom select pin (csboot ) are disabled out of reset. there are twelve chip-select functions and only eight associated data bus pins. there is not a one-to-one correspondence. refer to 4.8.4 chip-select reset operation for more detailed information. the csboot signal is normally enabled out of reset. the state of the data0 line dur- ing reset determines what port width csboot uses. if data0 is held high (either by the weak internal pull-up driver or by an external pull-up device), 16-bit width is select- ed. if data0 is held low, 8-bit port size is selected. table 4-19 chip-select pin functions 16-bit chip select 8-bit chip select alternate function discrete output csboot csboot csboot ? cs0 cs0 br ? cs1 cs1 bg ? cs2 cs2 bgack ? cs3 cs3 fc0 pc0 cs4 cs4 fc1 pc1 cs5 cs5 fc2 pc2 cs6 cs6 addr19 pc3 cs7 cs7 addr20 pc4 cs8 cs8 addr21 pc5 cs9 cs9 addr22 pc6 cs10 cs10 addr23 eclk table 4-20 pin assignment field encoding bit field description 00 discrete output 01 alternate function 10 chip select (8-bit port) 11 chip select (16-bit port)
motorola system integration module mc68331 4-52 user? manual 4 a pin programmed as a discrete output drives an external signal to the value specified in the pin data register. no discrete output function is available on pins csboot , br , bg , or bgack . addr23 provides eclk output rather than a discrete output signal. when a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate dsack or avec internally on an ad- dress and control signal match. 4.8.1.2 chip-select base address registers each chip select has an associated base address register. a base address is the low- est address in the block of addresses enabled by a chip select. block size is the extent of the address block above the base address. block size is determined by the value contained in a blksz field. block addresses for different chip selects can overlap. the blksz field determines which bits in the base address field are compared to cor- responding bits on the address bus during an access. provided other constraints de- termined by option register fields are also satisfied, when a match occurs, the associated chip-select signal is asserted. table 4-21 shows blksz encoding. the chip-select address compare logic uses only the most significant bits to match an address within a block. the value of the base address must be a multiple of block size. base address register diagrams show how base register bits correspond to address lines. after reset, the mcu fetches the initialization routine from the address contained in the reset vector, located beginning at address $000000 of program space. to support bootstrap operation from reset, the base address field in chip-select base address reg- ister boot (csbarbt) has a reset value of all zeros. a memory device containing the reset vector and initialization routine can be automatically enabled by csboot after a reset. the block size field in csbarbt has a reset value of 512 kbytes. refer to 4.8.4 chip-select reset operation for more information. 4.8.1.3 chip-select option registers option register fields determine timing of and conditions for assertion of chip-select signals. to assert a chip-select signal, and to provide dsack or autovector support, other constraints set by fields in the option register and in the base address register must also be satisfied. table 4-22 is a summary of option register functions. table 4-21 block size encoding blksz[2:0] block size address lines compared 000 2 kbyte addr[23:11] 001 8 kbyte addr[23:13] 010 16 kbyte addr[23:14] 011 64 kbyte addr[23:16] 100 128 kbyte addr[23:17] 101 256 kbyte addr[23:18] 110 512 kbyte addr[23:19] 111 1 mbyte addr[23:20]
mc68331 system integration module motorola user? manual 4-53 4 *use this value when function is not required for chip-select operation. the mode bit determines whether chip-select assertion simulates an asynchronous bus cycle, or is synchronized to the m6800-type bus clock signal (eclk) available on addr23 (refer to 4.3 system clock for more information on eclk). the byte field controls bus allocation for chip-select transfers. port size, set when a chip select is enabled by a pin assignment register, affects signal assertion. when an 8-bit port is assigned, any byte field value other than %00 enables the chip select signal. when a 16-bit port is assigned, however, byte field value determines when the chip select is enabled. the byte fields for cs[10:0] are cleared during reset. how- ever, both bits in the boot rom option register (csorbt) byte field are set (%11) when the reset signal is released. the r/w field causes a chip-select signal to be asserted only for a read, only for a write, or for both read and write. use this field in conjunction with the strb bit to gen- erate asynchronous control signals for external devices. the strb bit controls the timing of a chip-select assertion in asynchronous mode. se- lecting address strobe causes a chip-select signal to be asserted synchronized with the address strobe. selecting data strobe causes a chip-select signal to be asserted synchronized with the data strobe. this bit has no effect in synchronous mode. the dsack field specifies the source of data strobe acknowledge signals used in asynchronous mode. it also allows the user to optimize bus speed in a particular ap- plication by controlling the number of wait states that are inserted. the space field determines the address space in which a chip select is asserted. an access must have the space type represented by space encoding in order for a chip- select signal to be asserted. the ipl field contains an interrupt priority mask that is used when chip-select logic is set to trigger on external interrupt acknowledge cycles. when the space field is set table 4-22 option register function summary mode byte r/w strb dsack space ipl avec 0 = async* 00 = disable 00 = rsvd 0 = as 0000 = 0 wait 00 = cpu sp 000 = all* 0 = off* 1 = sync 01 = lower 01 = read 1 = ds 0001 = 1 wait 01 = user sp 001 = priority 1 1 = on 10 = upper 10 = write 0010 = 2 wait 10 = supv sp 010 = priority 2 *11 = both 11 = both 0011 = 3 wait 11 = s/u sp* 011 = priority 3 0100 = 4 wait 100 = priority 4 0101 = 5 wait 101 = priority 5 0110 = 6 wait 110 = priority 6 0111 = 7 wait 111 = priority 7 1000 = 8 wait 1001 = 9 wait 1010 = 10 wait 1011 = 11 wait 1100 = 12 wait 1101 = 13 wait 1110 = f term 1111 = external
motorola system integration module mc68331 4-54 user? manual 4 to %00 (cpu space), interrupt priority (addr[3:1]) is compared to ipl value. if the val- ues are the same, and other option register constraints are satisfied, a chip select sig- nal is asserted. this field only affects the response of chip selects and does not affect interrupt recognition by the cpu. encoding %000 causes a chip-select signal to be as- serted regardless of interrupt acknowledge cycle priority, provided all other constraints are met. the avec bit selects one of two methods of acquiring an interrupt vector during an external interrupt acknowledge cycle. the internal autovector signal is generated only in response to interrupt requests from the sim irq pins. 4.8.1.4 portc data register the portc data register latches data for portc pins programmed as discrete out- puts. when a pin is assigned as a discrete output, the value in this register appears at the output. pc[6:0] correspond to cs[9:3] . bit 7 is not used. writing to this bit has no effect, and it always reads zero. 4.8.2 chip-select operation when the mcu makes an access, enabled chip-select circuits compare the following items: 1. function codes to space fields, and to the ipl field if the space field encod- ing is not for cpu32 space. 2. appropriate addr bits to base address fields. 3. read/write status to r/w fields. 4. addr0 and/or siz bits to the byte field (16-bit ports only). 5. priority of the interrupt being acknowledged (addr[3:1]) to ipl fields (when the access is an interrupt acknowledge cycle). when a match occurs, the chip-select signal is asserted. assertion occurs at the same time as as or ds assertion in asynchronous mode. assertion is synchronized with eclk in synchronous mode. in asynchronous mode, the value of the dsack field de- termines whether dsack is generated internally. dsack also determines the number of wait states inserted before internal dsack assertion. the speed of an external device determines whether internal wait states are needed. normally, wait states are inserted into the bus cycle during s3 until a peripheral as- serts dsack . if a peripheral does not generate dsack , internal dsack generation must be selected and a predetermined number of wait states can be programmed into the chip-select option register. refer to the sim reference manual (simrm/ad) for further information. 4.8.3 using chip-select signals for interrupt acknowledge ordinary i/o bus cycles use supervisor space access, but interrupt acknowledge bus cycles use cpu space access. refer to 4.5.4 cpu space cycles for more informa- tion. there are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle.
mc68331 system integration module motorola user? manual 4-55 4 during a cpu space cycle, bits [15:3] of the appropriate base register must be config- ured to match addr[23:11], as the address is compared to an address generated by the cpu. figure 4-19 shows cpu space encoding for an interrupt acknowledge cycle. fc[2:0] are set to %111, designating cpu space access. addr[3:1] indicate interrupt priority, and the space type field (addr[19:16]) is set to %1111, the interrupt acknowledge code. the rest of the address lines are set to one. figure 4-19 cpu space encoding for interrupt acknowledge because address match logic functions only after the ebi transfers an interrupt ac- knowledge cycle to the external address bus following iarb contention, chip-select logic generates avec or dsack signals only in response to interrupt requests from external irq pins. if an internal module makes an interrupt request of a certain priority, and the chip-select base address and option registers are programmed to generate avec or dsack signals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates an internal dsack signal to terminate the cycle. perform the following operations before using a chip select to generate an interrupt ac- knowledge signal. 1. program the base address field to all ones. 2. program block size to no more than 64 kbytes, so that the address comparator checks addr[19:16] against the corresponding bits in the base address regis- ter. (the cpu32 places the cpu32 space type on addr[19:16].) 3. set the r/w field to read only. an interrupt acknowledge cycle is performed as a read cycle. 4. set the byte field to lower byte when using a 16-bit port, as the external vector for a 16-bit port is fetched from the lower byte. set the byte field to upper byte when using an 8-bit port. if an interrupting device does not provide a vector number, an autovector acknowledge must be generated. asserting avec , either by asserting the avec pin or by generat- ing avec internally using the chip-select option register, terminates the bus cycle. 4.8.4 chip-select reset operation the least significant bits of each of the 2-bit cs[10:0] pin assignment fields in cspar0 and cspar1 each have a reset value of one. the reset values of the most significant cpu space iack tim 11111111111111111111 1 111 level 19 16 23 function code 20 0 cpu space type field address bus interrupt acknowledge
motorola system integration module mc68331 4-56 user? manual 4 bits of each field are determined by the states of data[7:1] during reset. there are weak internal pull-up drivers for each of the data lines, so that chip-select operation will be selected by default out of reset. however, the internal pull-up drivers can be overcome by bus loading effects ?to insure a particular configuration out of reset, use an active device to put the data lines in a known state during reset. the base address fields in chip-select base address registers csbar[0:10] and chip select option regis- ters csor[0:10] have the reset values shown in table 4-23 . the byte fields of csor[0:10] have a reset value of ?isable? so that a chip-select signal cannot be as- serted until the base and option registers are initialized. following reset, the mcu fetches initial stack pointer and program counter values from the exception vector table, beginning at $000000 in supervisor program space. the csboot chip-select signal is used to select an external boot rom mapped to a base address of $000000. in order to do this, the reset values of the fields that control cs- boot must be different from those of other chip select signals. the msb of the csboot field in cspar0 has a reset value of one, so that chip-select function is selected by default out of reset. the byte field in option register csorbt has a reset value of ?oth bytes?so that the select signal is enabled out of reset. the lsb value of the csboot field, determined by the logic level of data0 during reset, selects boot rom port size. when data0 is held low during reset, port size is eight bits. when data0 is held high during reset, port size is 16 bits. data0 has a weak internal pull-up driver, so that a 16-bit port will be selected by default out of reset. how- ever, the internal pull-up driver can be overcome by bus loading effects ?to insure a particular configuration out of reset, use an active device to put data0 in a known state during reset. the base address field in chip-select base address register boot (csbarbt) has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the csboot signal is asserted. the block size field in csbarbt has a reset value of 1 mbyte. table 4-24 shows csboot reset values. table 4-23 chip select base and option register reset values fields reset values base address $000000 block size 2 kbyte async/sync mode asynchronous mode upper/lower byte disabled read/write reserved as /ds as dsack no wait states address space cpu space ipl any level autovector external interrupt vector
mc68331 system integration module motorola user? manual 4-57 4 4.9 parallel input/output ports fifteen sim pins can be configured for general-purpose discrete input and output. al- though these pins are organized into two ports, port e and port f, function assignment is by individual pin. pin assignment registers, data direction registers, and data regis- ters are used to implement discrete i/o. 4.9.1 pin assignment registers bits in the port e and port f pin assignment registers (pepar and pfpar) control the functions of the pins in each port. any bit set to one defines the corresponding pin as a bus control signal. any bit cleared to zero defines the corresponding pin as an i/o pin. 4.9.2 data direction registers bits in the port e and port f data direction registers (ddre and ddrf) control the di- rection of the pin drivers when the pins are configured as i/o. any bit in a register set to one configures the corresponding pin as an output. any bit in a register cleared to zero configures the corresponding pin as an input. these registers can be read or writ- ten at any time. writes have no effect. 4.9.3 data registers a write to the port e and port f data registers (porte and portf) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. a read of a data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. both data registers can be accessed in two lo- cations. registers can be read or written at any time. 4.10 factory test the test submodule supports scan-based testing of the various mcu modules. it is in- tegrated into the sim to support production test. test submodule registers are intend- ed for motorola use only. register names and addresses are provided in appendix d register summary to show the user that these addresses are occupied. the quot pin is also used for factory test. table 4-24 csboot base and option register reset values fields reset values base address $000000 block size 1 mbyte async/sync mode asynchronous mode upper/lower byte both bytes read/write read/write as /ds as dsack 13 wait states address space supervisor/user space ipl any level autovector interrupt vector externally
motorola system integration module mc68331 4-58 user? manual 4
mc68331 central processing unit motorola user? manual 5-1 5 section 5 central processing unit the cpu32, the instruction processing module of the m68300 family, is based on the industry-standard mc68000 processor. it has many features of the mc68010 and mc68020, as well as unique features suited for high-performance controller applica- tions. this section is an overview of the cpu32. for detailed information concerning cpu operation, refer to the cpu32 reference manual (cpu32rm/ad). 5.1 general ease of programming is an important consideration in using a microcontroller. the cpu32 instruction format reflects a philosophy emphasizing register-memory interac- tion. there are eight multifunction data registers and seven general-purpose address- ing registers. all data resources are available to all operations requiring those resources. the data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. word and long-word operations support address manipula- tion. although the program counter (pc) and stack pointers (sp) are special-purpose registers, they are also available for most data addressing activities. ease of program checking and diagnosis is further enhanced by trace and trap capabilities at the in- struction level. a block diagram of the cpu32 is shown in figure 5-1 . the major blocks operate in a highly independent fashion that maximizes concurrence of operation while managing the essential synchronization of instruction execution and bus operation. the bus con- troller loads instructions from the data bus into the decode unit. the sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit.
motorola central processing unit mc68331 5-2 user? manual 5 figure 5-1 cpu32 block diagram 5.2 cpu32 registers the cpu32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. user programs can use only the registers of the user model. the supervisor programming model, which supplements the user programming model, is used by cpu32 system programmers who wish to protect sen- sitive operating system functions. the supervisor model is identical to that of the mc68010 and later processors. the cpu32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register (see figure 5-2 and figure 5-3 ). instruction pipeline stage stage cb execution unit program counter section data section write pending buffer prefetch controller microbus controller address bus data bus bus control signals stage a microsequencer and control buffer decode control store control logic 1127a
mc68331 central processing unit motorola user? manual 5-3 5 figure 5-2 user programming model figure 5-3 supervisor programming model supplement 31 16 15 8 7 0 d0 d1 d2 d3 data registers d4 d5 d6 d7 31 16 15 0 a0 a1 a2 a3 address registers a4 a5 a6 31 16 15 0 a7 (usp) user stack pointer 31 0 pc program counter 70 ccr condition code register 31 16 15 0 a7?(ssp) supervisor stack pointer 15 8 7 0 (ccr) sr status register 31 0 vbr vector base register 20 sfc alternate function dfc code registers
motorola central processing unit mc68331 5-4 user? manual 5 5.2.1 data registers the eight data registers can store data operands of 1,8, 16, 32, and 64 bits and ad- dresses of 16 or 32 bits. the following data types are supported: ?bits ?packed binary-coded decimal digits ?byte integers (8 bits) ?word integers (16 bits) ?long-word integers (32 bits) ?quad-word integers (64 bits) each of data registers d7?0 is 32 bits wide. byte operands occupy the low-order 8 bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits. when a data register is used as either a source or destination operand, only the ap- propriate low-order byte or word (in byte or word operations, respectively) is used or changed; the remaining high-order portion is unaffected. the least significant bit (lsb) of a long-word integer is addressed as bit zero, and the most significant bit (msb) is addressed as bit 31. figure 5-4 shows the organization of various types of data in the data registers. quad-word data consists of two long words and represents the product of 32-bit mul- tiply or the dividend of 32-bit divide operations (signed and unsigned). quad-words may be organized in any two data registers without restrictions on order or pairing. there are no explicit instructions for the management of this data type, although the movem instruction can be used to move a quad-word into or out of the registers. binary-coded decimal (bcd) data represents decimal numbers in binary form. cpu32 bcd instructions use a format in which a byte contains two digits. the four lsb con- tain the least significant digit, and the four msb contain the most significant digit. the abcd, sbcd, and nbcd instructions operate on two bcd digits packed into a single byte.
mc68331 central processing unit motorola user? manual 5-5 5 figure 5-4 data organization in data registers 5.2.2 address registers each address register and stack pointer is 32 bits wide and holds a 32-bit address. ad- dress registers cannot be used for byte-sized operands. therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size. when an address register is used as the destination operand, the entire register is affected, regardless of the op- eration size. if the source operand is a word size, it is sign-extended to 32 bits. ad- dress registers are used primarily for addresses and to support address computation. the instruction set includes instructions that add to, subtract from, compare, and move the contents of address registers. figure 5-5 shows the organization of addresses in address registers. figure 5-5 address organization in address registers 31 30 10 msb lsb byte 31 24 23 16 15 8 7 0 high-order byte middle high byte middle low byte low-order byte 16-bit word 31 16 15 0 high-order word low-order word long word 31 0 long word quad-word 63 62 32 msb any dx 31 10 any dy lsb 31 16 15 0 sign extended 16-bit address operand 31 0 full 32-bit address operand
motorola central processing unit mc68331 5-6 user? manual 5 5.2.3 program counter the pc contains the address of the next instruction to be executed by the cpu32. dur- ing instruction execution and exception processing, the processor automatically incre- ments the contents of the pc or places a new value in the pc as appropriate. 5.2.4 control registers the control registers described in this section contain control information for supervi- sor functions and vary in size. with the exception of the condition code register (the user portion of the status register), they are accessed only by instructions at the su- pervisor privilege level. 5.2.4.1 status register the status register (sr) stores the processor status. it contains the condition codes that reflect the results of a previous operation and can be used for conditional instruc- tion execution in a program. the condition codes are extend (x), negative (n), zero (z), overflow (v), and carry (c). the user (low-order) byte containing the condition codes is the only portion of the sr information available at the user privilege level; it is referenced as the condition code register (ccr) in user programs. at the supervisor privilege level, software can access the full status register. the upper byte of this register includes the interrupt priority (ip) mask (three bits), two bits for placing the processor in one of two tracing modes or disabling tracing, and the super- visor/user bit for placing the processor at the desired privilege level. undefined bits in the status register are reserved by motorola for future definition. the undefined bits are read as zeros and should be written as zeros for future compatibility. all operations to the sr and ccr are word-size operations, but for all ccr operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level. refer to appendix d register summary for bit/field definitions and a diagram of the status register. 5.2.4.2 alternate function code registers alternate function code registers (sfc and dfc) contain 3-bit function codes. func- tion codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-mbyte address spaces. the processor automatically gen- erates function codes to select address spaces for data and programs at the user and supervisor privilege levels and to select a cpu address space used for processor functions (such as breakpoint and interrupt acknowledge cycles). registers sfc and dfc are used by the moves instruction to specify explicitly the function codes of the memory address. the movec instruction is used to transfer val- ues to and from the alternate function code registers. this is a long-word transfer; the upper 29 bits are read as zeros and are ignored when written.
mc68331 central processing unit motorola user? manual 5-7 5 5.2.5 vector base register (vbr) the vbr contains the base address of the 1024-byte exception vector table, consist- ing of 256 exception vectors. exception vectors contain the memory addresses of rou- tines that begin execution at the completion of exception processing. refer to 5.9 exception processing for more information on the vbr and exception processing. 5.3 memory organization memory is organized on a byte-addressable basis in which lower addresses corre- spond to higher order bytes. for example, the address n of a long-word data item cor- responds to the address of the most significant byte of the highest order word. the address of the most significant byte of the low-order word is n + 2, and the address of the least significant byte of the long word is n + 3. the cpu32 requires long-word and word data and instructions to be aligned on word boundaries (refer to figure 5-6 ). data misalignment is not supported.
motorola central processing unit mc68331 5-8 user? manual 5 figure 5-6 memory operand addressing bit data 1 byte = 8 bits integer data 1 byte = 8 bits 76543210 msb = most significant bit lsb = least significant bit address 1 address = 32 bits long word = 32 bits word = 16 bits 15 0 word 1 word 2 high order low order msb lsb 0 lsb msb 15 msd = most significant digit lsd = least significant digit decimal data bcd digits = 1 byte 15 12 11 8 7 4 3 0 msd bcd 0 bcd 4 bcd 1 bcd 5 bcd 2 bcd 6 bcd 3 bcd 7 high order low order msb byte 0 lsb byte 1 byte 2 byte 3 15 8 7 0 15 0 msb word 0 lsb lsd 1125a address 1 address 2 address 0 long word 0 long word 1 long word 2
mc68331 central processing unit motorola user? manual 5-9 5 5.4 virtual memory the full addressing range of the cpu32 on the mc68331 is 16 mbytes in each of eight address spaces. even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 mbytes of memory available to each user program by using virtual memory techniques. a system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device. when the processor at- tempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. the access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. the suspended access is then restarted or continued. the cpu32 uses instruction restart, which requires that only a small portion of the in- ternal machine state be saved. after correcting the fault, the machine state is restored, and the instruction is fetched and started again. this process is completely transpar- ent to the application program. 5.5 addressing modes addressing in the cpu32 is register-oriented. most instructions allow the results of the specified operation to be placed either in a register or directly in memory. there is no need for extra instructions to store register contents in memory. there are seven basic addressing modes: ?register direct ?register indirect ?register indirect with index ?program counter indirect with displacement ?program counter indirect with index ?absolute ?immediate the register indirect addressing modes include postincrement, predecrement, and off- set capability. the program counter indirect mode also has index and offset capabili- ties. in addition to these addressing modes, many instructions implicitly specify the use of the status register, stack pointer, and/or program counter. 5.6 processing states the processor is always in one of four processing states: normal, exception, halted, or background. the normal processing state is associated with instruction execution; the bus is used to fetch instructions and operands and to store results. the exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. the exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruc- tion. exception processing can be forced externally by an interrupt, a bus error, or a reset.
motorola central processing unit mc68331 5-10 user? manual 5 the halted processing state is an indication of catastrophic hardware failure. for ex- ample, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. the background processing state is initiated by breakpoints, execution of special in- structions, or a double bus fault. background processing is enabled by pulling bkpt low during reset . background processing allows interactive debugging of the sys- tem via a simple serial interface. 5.7 privilege levels the processor operates at one of two levels of privilege: user or supervisor. not all in- structions are permitted to execute at the user level, but all instructions are available at the supervisor level. effective use of privilege level can protect system resources from uncontrolled access. the state of the s bit in the status register determines the privilege level and whether the user stack pointer (usp) or supervisor stack pointer (ssp) is used for stack operations. 5.8 instructions the cpu32 instruction set is summarized in table 5-1 . the instruction set of the cpu32 is very similar to that of the mc68020. two new instructions have been added to facilitate controller applications: low-power stop (lpstop) and table lookup and in- terpolate (tbls, tblsn, tblu, tblun). the following mc68020 instructions are not implemented on the cpu32: bfxxx bit field instructions (bfchg, bfclr, bfexts, bfextu, bfffo, bfins, bfset, bftst) callm, rtm ?call module, return module cas, cas2 ?compare and swap (read-modify-write instructions) cpxxx ?coprocessor instructions (cpbcc, cpdbcc, cpgen, cprestore, cpsave, cpscc, cptrapcc) pack, unpk ?pack, unpack bcd instructions memory ?memory indirect addressing modes the cpu32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to de- fine special purpose functions. however, motorola reserves the right to use all current- ly unimplemented instruction operation codes for future m68000 core enhancements.
mc68331 central processing unit motorola user? manual 5-11 5 table 5-1 instruction set summary instruction syntax operand size operation abcd dn, dn? (an), ?(an) 8 8 source 10 + destination 10 + x t destination add dn, , dn 8, 16, 32 8, 16, 32 source + destination t destination adda , an 16, 32 source + destination t destination addi #, 8, 16, 32 immediate data + destination t destination addq #, 8, 16, 32 immediate data + destination t destination addx dn, dn (an), ?(an) 8, 16, 32 8, 16, 32 source + destination + x t destination and , dn dn, 8, 16, 32 8, 16, 32 source ?destination t destination andi #, 8, 16, 32 data ?destination t destination andi to ccr #, ccr 8 source ?ccr t ccr andi to sr 1 #, sr 16 source ?sr t sr asl dn, dn #, dn 8, 16, 32 8, 16, 32 16 asr dn, dn #, dn 8, 16, 32 8, 16, 32 16 bcc
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